Block Flow allows you
to create a design that can be defined as a unique block for immediate
instantiation into a design and/or be preserved and set aside for future
use. A completed block is optimized using the customary synthesis, simulation
and place-and-route flows, and may or may not include I/Os. Placement
of components within the block and timing are preserved. When creating
a new project in Libero or Designer, select a "Block Design Flow" instead
of a standard flow, after which the block can be published to a repository.
The block can then be instantiated into a design using the conventional
Libero design flow. Libero IDE v7.3 Block Design supports Fusion, IGLOO,
ProASIC3, Axcelerator, and RTAX-S family devices.
Libero IDE now
supports designs with mixed VHDL and Verilog source files. Libero
will pass libraries and generate netlists in your preferred HDL format.
Synplify Pro AE is needed for synthesis and ModelSim PE/SE
(full feature version from Mentor) is needed to run simulation on a
mixed HDL design.
HDL Templates for Verilog or VHDL
for quick insertion into the HDL code. Various HDL templates
are in a library of HDL command statements that can be copied or automatically
inserted into the HDL design in the text editor window. A "Templates
Window" makes it easy to view, copy, or insert from a large list,
which includes commands such as "insert synthesis attributes/directives", "wait
statement", or "port declaration".
SmartGen Enhancements for Fusion
Analog System Builder (ASB)
- Fusion NGMUX macro enhancement: A second clock input
of the NGMUX is now allowed to drive the NGMUX input as well as other
core logic. This enhancement supports the Fusion Analog System use
model of continuously driving the ACM CLK with a slow clock ( < 10
MHZ ) and simultaneously driving the rest of the logic with a switching
fast/slow clock, without using an additional global resource.
- PreScaler On/Off Selection. The Voltage Monitor,
Current Monitor, and Differential Voltage Monitor configuration dialogs
have been updated to provide a option to select between using or bypassing
the prescaler. When the prescaler is selected, a tooltip shows what
prescaler value is being used for the configuration.
SmartTime
- Bottleneck Analysis: A bottleneck is a point in
the design that contributes to multiple failing paths. This new 7.3
feature finds and lists all bottlenecks according to severity and occurrences.
The list has a format similar to the existing "datasheet" report.
- Clock Analysis for Virtual Clocks: In some cases,
paths from one FPGA may sensitize or be sensitized by paths outside
the FPGA (e.g. on the board, or on another FPGA.) The new Virtual Clock
capability in SmartTime 7.3 enables you to specify a constraint for
a clock that is running outside the FPGA, and thus do timing analysis
on the design as it interacts with this "virtual" circuitry.
SmartTime Timing
Changes
- A3P timing is updated, now based on the silicon
characterization. This update includes all A3P devices except the
A3PE600. The impact on timing for existing designs is minimal.
- Enhanced Min Delay (EMD) support for ProASIC3 -
SmartTime now provides support for precise minimum delay/hold-time
analysis based on A3P characterized silicon timing data. This new
feature eliminates the need to over guard-band a design for minimum
delay, providing a more comprehensive, precise way to perform chip-to-chip
evaluation of external setup/hold and clock-to-out timing.
- UFROM Clock-to-Out timing has been extended for
A3P250 and A3P1000 devices. If your A3P250 or A3P1000 design includes
a UFROM, re-run SmartTime to obtain the correct timing information.
- FIFO Write Enable (WEN) and Read Enable (REN) setup time is
increased by a depth dependent delay to better align with the silicon
capability. (A3P250 and AFS600 Rev A/B)
- IBIS model for the APA1000 FG896 is updated to include
support for MIL temperature.
SmartPower
- Initialization with SmartTime Timing Constraints – links
SmartPower to SmartTime. For each clock in SmartPower, the equivalent
clock and its constraints are found in SmartTime. The power is then
calculated using the user's actual timing constraints. This approach
gives a more accurate view of the power consumption based on actual
expected operating frequencies, and enables the user to keep frequency
information between SmartTime and SmartPower in synch.
- Advanced Power Analysis for Fusion – Now includes
analysis for all Fusion-specific low-power modes
- adds Analog Block, Embedded Flash Memory, RC and Crystal (XTL)
Oscillators to "Type"
- adds VCC3.3A analog to "Rail"
- analyzes power contribution for the A/D converter Quad blocks
- Advanced Power Analysis for Memories – This
feature adds the capability to view power consumption for memory blocks
such as RAM, FIFO and embedded flash memory based on specifics of the
memories, such as number of active bits, aspect ratio of the memory
blocks, the number of memory blocks, etc.
- An Instance Properties Pop-Up box can be accessed
with a right click on any instance in the Analysis Tab. The pop-up
box provides detailed information about the selected instance.
- Improved Thermal Analysis and Static Power Calculation:
Static Power calculation is now based on Junction Temperature. Two
modes are available:
- Mode 1: Tjunction is stable as a function of Operating Condition
only. The Operating Condition can be changed in the preferences window.
- Mode 2: The user changes Tambient and the Thermal-resistance is
used to compute T-junction. If the estimated T-junction exceeds the
Maximum of the range, a warning is issued
WaveFormer Lite Analog Test
Benches for Fusion
- WaveFormer Lite v11.11d includes analog waveform creation for Fusion
design test benches. Various pre-defined analog waveforms are available
from the Signal Properties Dialog such as Sinusoidal, Step, Increment,
Random, Capacitor charge/discharge. For a given input, the testbench
is created by specifying or creating the waveform type and then defining
the specific duration, period, and signal height requirement.
Synplify/Synplify Pro 8.6.2H
- Supports the Fusion AFS1500
- Supports IGLOO devices (not including the AGL030).
- RAM inferencing is now available for A3P. Synplify/Pro
AE can automatically infer synchronous RAMs from your HDL (Verilog
or VHDL) source code and, where appropriate generate technology-specific
single or dual-port RAMs.
- AX RAM/FIFO Timing: The timing models for Axcelerator
RAMs and FIFOs are more accurate.
- AX I/O Attribute synthesis support: The 8.62b SCOPE
constraint editor allows you to specify an I/O standard (LVTTL, LVCMOS,
etc) and set the attributes such as drive strength, slew rate, and
termination. The software stores the pad type specification and the
parameter values in the syn_padtype attribute. When you synthesize
your design, the I/O specifications are mapped to the appropriate I/O
pads within the technology.
- Advanced Fanout Control provides 3 different levels of fanout.
You can use the syn_maxfan attribute to control the
maximum fanout of the design, or an instance, net, or port.
Synplicity Identify AE
RTL Debugger can now be launched from Libero IDE. The Identify
tool has two functions: "Instrumentor" and "Debugger".
The Instrumentor is launched from within Synplify/Synplify Pro. The
Debugger can be launched from an Icon button on Libero IDE, however
you must have Synplify or Synplify Pro selected in your tool profiles
in order for the Debugger Icon to be visible on the Libero IDE Design
Flow Window (60878), following program file generation. Identify 2.4.1
is available separately as download from http://www.actel.com/download/program_debug/identify/files.aspx
, and licenses are free from Actel's Free License website. This version
supports Actel's ProASICPLUS, ProASIC3, and Fusion
family devices.
Precision 2006a Synthesis with
Actel FPGA device support is now available. Precision 2006a can be downloaded from
Actel's website. Free 45 day evaluation licenses are available at http://www.mentor.com/rd/actel-eval.
Precision 2006a supports Actel families except Fusion and IGLOO. Fusion
and IGLOO support is planned for Precision 2007a that will be released
in March 2007.
FlashPro 5.1
- This software will allow the generation of chained STAPL files for
Fusion devices as well as ARM-enabled Fusion and ProASIC3 devices.
In addition, the software will read a chained STAPL file to program
a complex chain of devices containing Fusion or ARM-enabled Fusion
and ARM-enabled ProASIC3 devices.
Silicon Explorer 5.2
- Adds support for RTAX4000S
New Devices and
Packages
| Family |
New Devices |
New Packages |
Package Updates |
| ProASIC3 |
A3P030 QFN132
A3P030 VQ100 |
A3PE1500 FG484
A3PE1500 FG676 |
A3PE1500 PQ208 * |
| IGLOO |
AGL030 VQ100
AGL030 QN132 |
- |
- |
| Fusion |
M7AFS1500 FG256 |
- |
AFS1500 FG256 |
* Current designs will be invalidated and must
be re-compiled and re-run through P&R.
RTAX-S Program File Generation
Dialog modified to provide Original Programming Algorithm (OPA) or
UMC Modified Algorithm (UMA) options (61264)
The Program File Generation User Interface for RTAX-S is enhanced to
accommodate a new programming algorithm (AFM) to be used for UMC production
devices. The "Fuse Export Options" UI Dialog Box now provides
selections for either OPA or UMA AFM generation. The specific device
selections are:
- RTAX4000S: UMA support only
- RTAX250S, RTAX1000S, RTAX2000S: UMA and OPA support
- Default selection is for OPA AFM generation
New Macros
Pipelined FIFO has been added for Axcelerator devices. The details are
included in the Macro
Guide.
Online Help
61973 - Online Help on Linux and Solaris Operating
Systems does not include 7.3 updates. Online Help contains
Libero/Designer v7.2 SP1 Content. For Libero/Designer v7.3 help, please
refer to the PDF files included with your v7.3 installation. Go to
the Help menu and select "Reference Manuals".
Installation
62568 – "ViewDraw" Libraries checkbox
visible during Solaris/Linux Installation.
ViewDraw is not a component that is available in Libero Solaris or Linux
OS editions. You should ignore this checkbox when the "Choose Install
Set" menu is visible.
ViewDraw
58929/58930 – Wir
file is not created by ViewDraw (All Devices)
Synthesis
64320 - Insertion of an inverter on enable signal of Fusion I/Os
For the Fusion family, the models used by Synplify for tristatable outputs have active low enable signals. However, AFS devices have active high enable signals so an inverter is erroneously inserted during synthesis and will cause the I/O to be tristated when it should be active and vice versa. This has been confirmed for the AFS family and versions 8.6.2H and 8.8.0 of Synplify. This problem does not affect the A3P/E family.
Solution/Workaround: Synplicity plans to implement a fix for this problem in the next release, Synplify 8.8.1. There are two recommended workarounds for this issue 1. Instantiate TRIBUFF or BIBUF macros in the RTL 2. Manually edit the netlist generated by Synplify to remove the inverter and associated net.
60977/61761 - Synplify/Synplify Pro AE 8.6.2H
does not include support the following devices that are supported in
Libero 7.3:
- A3P030. Use A3P125 for synthesis, and retarget back to A3P030 when
importing into Designer.
- AGL030. Use AGL125 for synthesis, and retarget back to AGL030 when
importing into Designer.
- M7A3P400. Use M7A3P600 for synthesis, and retarget back to M7A3P400
when importing into Designer.
- M7AFS1500. Use M7AFS600 for synthesis, and retarget back to M7AFS1500
when importing into Designer.
61950 - Synplify/Synplify Pro AE v8.6.2H.
The "HELP" for this version is not updated to include IGLOO/e
support. Refer to ProASIC3/E help for information.
61198 - Synplify fails to find references to
undefined modules since both the A500K and APA point to proasic.v library.
Workaround: User has to specify the file <Synplify_install_path>/lib/proasic/proasicplus.v
at the top of the file list passed to the synthesis tool.
60800 - An integer value (100) is mapped in
the post synthesis netlist for a real valued parameter (VCOFREQUENCY).
This only occurs in VHDL. (All Devices)
Libero IDE (Project Manager)
61449 - Libero 7.3 does not handle "Configuration
Statements" from the HDL Templates list.
The template 'Configuration Statements' can be used in the HDL code by
Synplify or ModelSim, however these Configuration Statements
are ignored by Libero's HDL parser. The Design Hierarchy will not be
updated based on the Configuration Statements present in the HDL source
code.
61452 - The Export Template does not distinguish
between VHDL and Verilog Templates. As a result, a Verilog
Template file is exported with a VHDL file extension (.vhd). To export
a Verilog Template, enter the template name with the file extension
.v. Otherwise Libero by default will add the extension .vhd instead
of .v.
61661 - SmartGen generated EDAC core can not
be set as root (AX) (Linux and Solaris OS)
When creating and regenerating an EDAC core in SmartGen you will get
the following error in the IDE log window:
Error: "cannot be set as root. Schematic flow is only
supported on Windows"
Workaround: Set the root to the top-level file
instead of the EDAC RAM
61573 - Refresh
the Design Hierarchy if some files are not passed to Synthesis (All
Devices)
59754/61577 - VHDL
Instantiation with Verilog Top Level cannot be placed in Custom Library (All
Devices)
Block Design Flow
59174/60119 - Generics
and Parameters are not supported in Block instantiation in the Top
level Design (All Devices)
60369 - Do not instantiate a Block component
more than once.
The Block flow in 7.3 is limited to one instantiation of the block. Libero
does not issue a warning if more than one block is instantiated into
the design, however Designer will fail when the netlist is compiled.
Instantiating multiple blocks in the block flow is a future enhancement.
Mixed HDL Flow
59441/61579 - Designer
produces error when supplied with post-synthesis Verilog netlist in
Mixed HDL mode (All Devices)
60261/61578 - ModelSim gives
error "Could not find proasic3e.vtables" (ProASIC3/E)
Identify AE
59205/61580 - Keeping
the word '_identify' in the new Identify implementation name (All
Supported Devices)
60930/61575 - Identify
cannot instrument a netlist generated from ViewDraw (All Supported
Devices)
60667 - Drop
down menu "Launch Identify" is grayed out in Synplify AE (All
Supported Devices)
60929/61574 - Identify
Debugger does not work with design that is instrumented by later version
of Identify Instrumentor (All Supported Devices)
PALACE
61576 - Palace
cannot be used to optimize the instrumented design
Designer
60732 - Export
SDF TCL command failure (All Devices)
61444 - Spine
support is disabled on A3P030 and AGL030 devices
62374 - Syntax error in STAPL player when using
encrypted files (A3P/E, AFS)
An encrypted A3P/E, AFS, M7 STAPL file is not compatible with Actel's
STAPL player. A syntax error will occur when the file is executed through
the player. FlashPro and Sculptor software are not affected.
Designer Compile
61348 - Designer
compile error message does not reflect AGL030 RAM support correctly
62092 - A3P030 or AGL030 designs in the VQ100
package do not support all 6 CLKBUFs. A design that contains
6 CLKBUFs using this die and package will issue a compile error. Only
5 CLKBUFs can be instantiated at this time.
SmartGen
61893 - SmartGen does not differentiate core
selections for A3P030/AGL030. A3P030 and AGL030 devices do
not contain PLLs, RAMs, or FIFOs. (see specifications for these devices
at http://www.actel.com/products/igloo/ and http://www.actel.com/products/pa3/).
When designing with these devices, SmartGen includes PLLs, RAMs, and
FIFOs in the available cores list, and the devices can be selected
and configured for the design, but the design will fail later in the
flow. Do not select these cores when using these devices.
MultiView Navigator (MVN)
62087 - Incorrect count of I/O region resources
for A3P/E and IGLOO/e. The IO resource count (region properties)
is counting the unbounded IO as an available IO resource.
Workaround: There is no impact on user really
since the Design Rule Check (DRC) will not allow you to do any assignments
to the unbonded I/Os. This issue is only a resource display issue.
62086 - Properties dialog box shows incorrect
ADLIB name for the User Low Static ICC (ULSICC) core. (IGLOO/e) When
you right click and Select Properties on an instantiated ULSICC macro,
the name of the cell in the properties dialog in the MultiView Navigator
(MVN) appears as "ADLIB:UUSERB". It should appear as "ADLIB:ULSICC".
Workaround: The tooltip in the MVN shows the
correct cell name.
62462 - Show Routes option is not functional
in v7.3 (ProASIC/ProASICPLUS)
The "Show Routes" option in the MVN, which has been functional
in previous versions, is not functional in v7.3. The RatsNest display
however is functional. This issue will be fixed in an upcoming release
SmartTime
62341 - External setup/hold displayed in the
Summary have a wrong value (All Families)
The worst external recovery value for a clock domain is set instead of
the worst external setup value in the summary (in the GUI and the timing
report) when the clock domain has an external recovery and removal/recovery
checks are enabled.
Workaround: The correct external setup values
are displayed in the list of paths.
Disabling removal/recovery checks will fix the values in the summary.
62342 - The datasheet does not show the external
setup information for generated clock domains (All Families)
The SmartTime datasheet does not show the external setup information
for the registers which have the generated clock as their clock source.
The SmartTime datasheet should show external setup information with respect
to the external clock.
62344 - LVDS clocks are not shown under the
Explicit Clock (A3P/E)
Differential input signals have two inputs, which are joined by a buffer.
This causes the potential clock to be ignored. In the SmartTime Add Clock
interface, you can add the output of the differential buffer using the
GUI, but it will not provide timing data for that path. Only adding the
individual differential pins will provide timing data for the path.
62345 - SmartTime shows false violation for
a path that does not exist (APA)
For nets and cells removed by Designer compile, SmartTime uses a 0 delay.
In some cases, this can lead to false min delay violations.
Workaround: Check the differences between
the optimized and the original netlist in netlist viewer to check if
it is a false path.
62346 - The Bottleneck Report "cost_type
- path_count" option is not working in Tcl (All Families)
A Tcl script "cost_type - path_count" does not work correctly.
The report will generate correctly using "cost_type - path_cost".
The option works correctly in the SmartTime Graphical User Interface.
62347 - Minimum Pulse Width is 0 for IO cells
in A3P030. This will only affect the maximum frequency for
clock domains without register-to-register paths or with short register-to-register
paths.
