Synplify AE 8.5f Synthesis
56484 – Synplify 8.53f synthesis does not support
AFS1500 device. Use AFS600. (Fusion)
*56628 – Manually
instantiate syn_noprune to the instance when using the ULSICC or VRPSM
macros. To synthesize the ULSICC macro, manually instantiate
syn_noprune to the instance to avoid the
macro being optimized out by Synplify AE. Synplify AE does this because
the ULSICC macro does not have any output port. (Fusion and ProASIC3/E)
A sample syntax is:
ULSICC I_ulsicc (.LSICC(LSICC_in) ) /* synthesis syn_noprune=1 */;
55821 – Incorrect
Port Declaration in ProASIC3.v and ProASIC3e.v libaries for RAM512x18
macros in Synlify v8.5F causes Synplify to optimize out the macro.
RAM512x18 macros are removed after synthesis using Synplify 8.5f
in A3P/E and M7A3P/E designs.
PALACE AE 3.3
56555 – PALACE 3.3 physical synthesis does
not support the AFS1500 device.
Synplify/ViewDraw
15199 – Synplify
issues warning messages about floating bus nets
Problem: When a schematic design with internal
buses gets synthesized, Synplify issues some warning messages about bus
nets that are floating. Actually some net assignments are missing in
the exported VHDL file.
For example an internal bus called MYBUS[3:0]. wir2ndb splits the bus into
four different nets:
MYBUS(3) <- which is the MSB
\MYBUS\
MYBUS_net_1
MYBUS_net_2 <- which is the LSB
Wir2ndb will reconstruct the local bus if all the bits are used (this
issue is fixed in 7.2) and the exported HDL file will show the following
bus declaration:
signal MYBUS : std_logic_vector(3 downto 0);
But the nets MYBUS(2), MYBUS(1) and MYBUS(0) are never used in the netlist.
Nets \MYBUS\, MYBUS_net_1 and MYBUS_net_2 are used instead. The synthesis
tool does not know that nets \MYBUS\ and MYBUS(2) are the same and then
some warning messages are reported.
Workaround: Hand modify the HDL netlist generated
by ndb2hdl
Manually add the following net assignments ate the beginning of the architecture:
General rule to find the nets extracted from the bus name:
Example: Consider the bus MYBUS[n:0]
ndb2hdl will declare the following signals:
MYBUS(n) <- which is the MSB
\MYBUS\
MYBUS_net_1
MYBUS_net_2
...
MYBUS_net_[n-2]
MYBUS_net_[n-1] <- which is the LSB
Manually add the following net assignments at the beginning of the architecture:
architecture DEF_ARCH of TOP is
...
begin
MYBUS(2) <= \MYBUS\;
MYBUS(1) <= MYBUS_net_1;
MYBUS(0) <= MYBUS_net_2;
...
Re-run your synthesis and the warning messages should be removed.
Note that there can have other naming conventions (There is a difference
if the net is connected to one port or many ports or if it is just an
internal net). However the purpose of this workaround is to provide a
general rule to find the nets and assign them to the correct bus bit.
Libero IDE Project Manager
55802 – Refresh the Design Hierarchy when modules
are defined in multiple files. If you have a design with the
same module defined in multiple files, and you want to modify the file,
select it from the Design Hierarchy window. The modification may have
an impact on the Design Hierarchy and it does not get updated accordingly.
Workaround: Refresh the Hierarchy display
either with CTRL+R, or from the EDIT => Refresh selection on the Libero
IDE Toolbar
55804 – HDL parser relies on the "use" clause
to find specific entities defined in a Library. After creating
a custom VHDL Library, You must use the "use" clause to select
a specific component entity within the library. For example, in a library
called "mylib", specify a component as follows:
Library mylib;
use mylib.<package>.all; or,
use mylib.all
Without the use clause the HDL parser cannot find an entity defined
in a custom VHDL library.
55807 – You
cannot use VHDL libraries defined in Libero in a testbench file. Stimulus
files are not parsed by the Libero IDE HDL parser, therefore a user
is not expected to use a VHDL library defined within Libero in the
testbench files. In Libero IDE v7.2, only user-defined VHDL libraries
are expected to be used with a testbench. Use the "organize stimulus" feature
to create correct .do files and simulate a design.
55766 – Do not use mixed-HDL designs. With
Libero IDE v7.2, you can import both VHDL and Verilog source files in
the same project. However, the mixed-HDL flow is not yet supported in
Libero IDE. You can use only one HDL type as source files (either VHDL
or Verilog).
56007 – Design Hierarchy does not show imported
modules. When the source files are imported using the New
Project Wizard, imported modules may not immediately be visible in
the Design Hierarchy. The files are correctly imported into the project.
Refresh the Libero IDE User Interface window either by using the shortcut
CTRL+R, or by using the Tool Bar menu, View -> Refresh Design Hierarchy.
All the modules should then be visible in the Design Hierarchy.
56003 – Design Hierarchy shows modules with
multiple definitions even though they are defined only once. The
Design Hierarchy tab can show module names under 'Modules defined in
multiple files' whereas they are defined only once in a single file.
56237 – Libero IDE User Interface freezes after
deleting or moving a project. If you create and save a project
in Libero IDE and then close Libero IDE, and consequently re-open Libero
IDE and create a new project, the Libero IDE User Interface may freeze
or hang. Use the Control R or Edit => Refresh from the Toolbar to
refresh the screen.
56165 – SmartGen log file can be moved to a
custom VHDL library. If you add a custom VHDL library into
the Libero IDE project and generate (for example) a 4-bit adder using
SmartGen, you may see from the File Manager that a pull-down 'Move
file(s) to library' is accessible from a right-click either on the
core .gen file or on the core .log file. Do not move the .gen or .log
file into the custom library. Only VHDL source files or VHDL stimulus
files should be moved into a custom VHDL library.
56427 – IP simulation files hard-coded to Package
File folder. Libero IDE v7.2 features the elimination of the
Package File Folder in the File Manager Window. VHDL package files
are now contained in the HDL Source Files directory. Libero IDE v7.2
detects the package files in the HDL Source Files directory and passes
them to the 3rd party tools. Actel IP (and possibly user projects)
have been hard-coded to go to the Package Folder for the simulation
(or other) files. While opening these projects in Libero IDE v7.2,
Libero IDE will create a background package directory and save a copy
of the package files in the HDL Source Files directory and the background
Package Directory. Users must not edit the files via the package directory.
Users should only edit package files using the Libero IDE text editor,
or if an external editor is used, Libero IDE must be open.
56552/55556 – Inappropriate Messages when opening
Analog System Builder (ASB) or Memory System Builder (MSB) core generated
using Libero/SmartGen v7.1. When opening ASB or MSB cores
that were generated using Libero IDE/SmartGen v7.1 with v7.1, you will
see many warning message such as "Unable to access file;
please check that the core file 'x_x_x' is valid; you may need to regenerate
this core." You should ignore these messages and regenerate the
cores:
- Open the Analog System or Memory System Core in SmartGen
- Double click on the Core in the "Configured Cores View"
- Click on Generate when the Analog System or Memory System Builder
UI comes up
51486/56591 – Libero
Project Manager considers a multiple definition for modules defined
by several schematic pages. When you have a single module "top" defined
in multiple schematic pages, Libero IDE considers that each schematic
page (e.g. top.x) redefines the same module "top", and will
produce an error message: "Error: The xxx module is defined in
multiple files. Duplicate modules are not supported. Select the file
you want to use from the Design Hierarchy. Error: The xxx module is
defined in multiple files. Duplicate modules are not supported. Select
the file you want to use from the Design Hierarchy." This error
is not expected because the multiple pages define one module called "top" and
not three separate modules called "top".
Workaround: When multi-page schematic modules
appear under "Modules defined in multiple pages" in the Design
Hierarchy tab", right click on the first schematic page (i..e. viewdraw/sch/
.1) and select "Use this file" in the pull down menu.
56618 – Post-synthesis HDL file may be generated
twice. Occasionally after running synthesis, you will see
duplicated messages in the log window:
Generating 'synthesis\PCI_DECODER.v'...
Done.
Generating 'synthesis\PCI_DECODER.v'...
Done.
In fact, the HDL file is generated twice in these cases. This issue
will be fixed in v7.2 SP1.
MultiView Navigator
56096 – Refresh issue when QCLK region deleted
through LCA. When you go to the Nets tab in the MultiView
Navigator and select a global net and then run Local Clock Assignment
on it, a region is created as expected.
Simulation
47177 – FIFO
simulation needs to be updated to reflect the glitch on FULL flag (Axcelerator)
SmartTime/Timing
54291/56077 – The "st_list_paths" TCL
Command Ignores the Number of Paths Set (All Families)
55820 – Violation
is reported when the slack is 0 (All Families)
54900 – Designer
crashes when executing a script with the st_restore command (All
Families)
54287/55856 – Generated
clock constraint is not honored after clock constraint been removed
then added back (Fusion)
54290/55833 – FIFO
Empty Flag Failing to De-Assert at Correct Time (Fusion, A3P/E)
AX/Timing
56392/56508 – FIFO setup time fix has impact
on performance based on FIFO depths. (Axcelerator, RTAX-S)
Axcelerator designs including embedded FIFOs may see a performance degradation
using Libero IDE/Designer v7.2. A change was made in v7.2 to correct
the Read and Write Enables with respect to the read and write clock.
Setup times have been adjusted incrementally based on FIFO depth. We
recommend that you run timing analysis to verify if the timing requirements
are still met after using Designer v7.2.
51587/54289 – AX
FIFO Empty Flag Failing to De-Assert at Correct Time (Axcelerator, RTAX-S)
CoreMP7
54292/55858 – ModelSim not
Loading CoreMP7 Bus Functional Model (Fusion M7AFS, M7A3P/E)
54293/54821 – CoreMP7
Designs with New UFROM Cannot be Placed in Designer. (Fusion M7AFS,
M7A3P/E)
54181 – CoreMP7 VHDL Support Changes have been
made in the Post-Synthesis VHDL Export of CoreMP7 Designs. Previously,
a double entity declaration existed of the A7S module (once in the
a7sBFM_TS_fusion.vhd and again in the VHD file generated by Synplicity),
which caused the following error in ModelSim:
# ** Error: (vsim-13) Recompile ../simulation/postsynth.YourTopLevelEntity
(def_arch) because ../simulation/postsynth.a7s has changed.
Comment the two lines below to change the architecture binding for the
entity A7S in the generated VHDL file which direct ModelSim to
use the architecture found in the a7sBFM_TS_fusion.vhd file:
-- for all : A7S
-- use entity work.A7S(DEF_ARCH);
SmartGen
56518 – Error generated when setting Dynamic
CCC (DYNCCC) using ClkA = 99 and Primary Frequency = 100. This
is only a problem using Dynamic CCC. Static CCC setup using the same
parameters functions properly. (A3P/E)
55550 – Analog System Builder Sample Sequencer
v7.2 Enhancement Issue for previous designs (Fusion).
Sample Sequences generated prior to v7.2 should be terminated with a
jump in 7.2. This is not a v7.2 issue, this is a requirement for designs
created prior to v7.2 that will also use v7.2
In the 7.2 Sequencer, the concept of "Procedures" has been
added to the Sample Sequencer User interface. A “Procedure” defines a
set of sequences and is independent from other Procedures. Procedure
sequences should terminate with a 'terminating' operation such as JUMP,
STOP, or POWERDOWN. A check is performed to ensure that a Procedure does
not over-run into another unrelated Procedure.
Previous versions of the SmartGen Analog System Builder (prior to v7.2)
allowed a sequence to be created w/o a terminating operation. Pre 7.2
generated cores that have sequences that end in a non-terminating operation
when imported into the 7.2 release of the Analog System Builder will
require modification if the core is to be regenerated. If you do not
need to regenerate the core, you can use the core as is without harm.
Voltage and Current Inputs:
Pre 7.2 generated cores only use 10 time slots to sample the voltage
and current inputs, and do not use the Jump operation. If an existing
design includes the voltage and current measurement functions in the
Analog System Builder, the cores should be regenerated using v7.2 to
be compliant. (Fusion)
56413 – On Demand Save and Read Pipeline combination
is an invalid configuration. When using the "Enable On
Demand Save to Flash Memory" function in configuring RAM in a
Fusion design, the “Read Pipeline” function should not be used. Do
not check the “Read Pipeline” checkbox. The Read Pipeline function
is not intended for use in combination with Enable On Demand Save.
(Fusion)
Axcelerator RAM Models
46209 – Axcelerator RAM Models, simultaneous
reading and writing of AX RAM to the same address. Prior to
v7.2, this would result in an indeterminate value being read from the
address, depending on the internal timing between the two operations
during that cycle. In v7.2, AX and RTAX-S simulation models were changed
to detect a read/write address match and to create a time slot around
the positive edge of WCLK/RCLK so that simultaneous read/write to the
same address will result in Read Data being driven to "X" after
one clock cycle.
Designer
54288/56155 – Designer/Smartgen
doesn't launch on a Linux 4.0 license server machine
55933 – Designer .adb implementation file not
showing in the Designer Place & Route box on the Libero IDE Design
Flow window. Under some circumstances after creating additional
Designer Views, the implementation .adb file is not visible in the
drop down box available on the Designer Place & Route button on
the Libero IDE Design Flow window. The implementation view .adb file
however is visible in the Libero IDE File Manager.
Workaround: Open the Designer .adb from the
File Manager and re-save.
56564 – IBIS support is not available for Fusion
devices. IBIS support will be available for Fusion devices
in a future release.
