Libero Project Manager
54284 - Libero
does not import all *.vhd files into the project for SmartGen generated
EDAC RAM on RTAX-S
Workaround: Manually import the RTL file into
Libero by using the File > Import menu.
54181 - Fusion CoreMP7 VHDL Simulation Error
Changes have been made in the Post-Synthesis VHDL Export of CoreMP7 Designs.
Previously, a double entity declaration existed of the A7S module (once
in the a7sBFM_TS_fusion.vhd and again in the VHD file generated by
Synplify), which caused the following error in ModelSim -
# ** Error: (vsim-13) Recompile ../simulation/postsynth.YourTopLevelEntity
(def_arch) because ../simulation/postsynth.a7s has changed.
Comment the two lines below to change the architecture binding for
the entity A7S in the generated VHDL file that direct ModelSim to
use the architecture found in the a7sBFM_TS_fusion.vhd file:
-- for all : A7S
-- use entity work.A7S(DEF_ARCH);
54583 - Similar to above (54181), a double entity
declaration existed of the A7S module (once in the a7sBFM_TS*.vhd and
again in the VHD file generated by PALACE), which causes the following
error in ModelSim -
# ** Error: (vsim-13) Recompile ../simulation/postsynth.YourTopLevelEntity
(def_arch) because ../simulation/postsynth.a7s has changed.
Comment the two lines below to change the architecture binding for
the entity A7S in the generated VHDL file which direct ModelSim to
use the architecture found in the a7sBFM_TS*.vhd file:
-- for all : A7S
-- use entity work.A7S(DEF_ARCH);
51925 - The
threshold flags related to the un-sampled channels do not show up in
the Analog Block top level Netlist
ViewDraw
53657 - The Scope attribute is no longer supported
for nets and components in ViewDraw. The radio button for local /global
scope has been removed from the net and component label dialogs.
PALACE 3.2
50945 - The post physical synthesis simulation fails
with CoreConsole Verilog project files (M7A3P/E). Verilog is case-sensitive.
PALACE 3.2 will generate an incorrect netlist where some letters are
in upper case instead of being lower-case. The work-around is, as an
example, change the following A7S I/O port names in the PALACE Verilog
netlist as follows: Replace NRESET by nRESET, DBGNTRST by DBGnTRST, NFIQ
by nFIQ, NIRQ by nIRQ, DBGNTDOEN by DBGnTDOEN, etc.
Designer
53764 - For Actel ProASIC3E and Fusion families, the
I/O standards SSTL 2.5v (Class I & II) and SSTL 3.3v (Class I & II),
drive strengths have been reduced based on silicon measurements. Note
that these updated drive values still meet all JEDEC SSTL IOH and IOL
requirements.
The 7.1 release of Libero/Designer has not been updated with this information;
it is planned to be updated in the 7.2 release. Output drive strengths
as represented in version 7.1 (“Estimated") and in version 7.2 (“Updated”)
are shown in the following table:
| |
Output Drive Strength Specification |
| Estimated |
Updated |
| SSTL 2.5V - Class I |
17 mA |
15 mA |
| SSTL 2.5V - Class II |
21 mA |
18 mA |
| SSTL 3.3V - Class I |
16 mA |
14 mA |
| SSTL 3.3V - Class II |
24 mA |
21 mA |
The Fusion datasheet
has been updated with the latest information. ProASIC3E datasheet will
be updated by 4/30/2006. Please refer to them for further details.
Fusion
53411 - Libero v7.1 will invalidate Fusion AFS250
ADBs created in Libero IDE v7.0 SP1 THAT USE THE MEMORY SYSTEM BUILDER.
All designs will be set back to the pre-compile state to correct a connectivity
mismatch in the Flash Memory Builder I/Os. You can save your layout and
constraints by using the Layout "Fixed" option and the "Keep
Existing" Physical Constraints check box ON in the Compile menu.
41646 - Cross-probing
a path from ChipPlanner to NetList Viewer function is not functional
Libero IDE/PALACE
53249 - Libero IDE v7.1 requires use of PALACE v3.2.
Older versions of PALACE can not be used with Libero IDE v7.1.
SmartGen
50657 - Memory System Builder will quit when you rapidly
click on the Start Address up/down arrow on Solaris and Linux OS. This
feature has been turned off on Solaris and Linux in v7.1.
54003 - Running
SmartGen On RedHat Linux Enterprise 3.0
54647 - In a Fusion design, SmartGen generates an incorrect
direction for port USER_DOUT for data storage clients in FlashMemory
System. This affects systems WITH ONE OR MORE DATA STORAGE CLIENTS. In
this case the OUTPUT port USER_DOUT is reversed as INPUT.
Workaround:
Verilog and VHDL Users:
- Change the direction of USER_DOUT as out in the top-level entity/module.
This step is the only change needed for Verilog.
VHDL users follow this additional step:
- Reverse the signal Assignment in the body just after BEGIN where
DOUT gets assigned to signal
In the case of designs with data storage + one or more AS, init or RAM
clients change
\USER_DOUT_TO_net[31]_net_1\ <= USER_DOUT(31);
TO
USER_DOUT(31) <= \USER_DOUT_TO_net[31]_net_1\;
In the case of designs with data storage clients only
\NVM_DAT_FROM_net[31]_net_1\ <= USER_DOUT(31);
TO
USER_DOUT(31) <= \NVM_DAT_FROM_net[31]_net_1\;
Change all the DOUT assignments in this manner.
For AFS090, DOUT is only 16 bits wide. For all other devices DOUT
is 32 bits wide.
SmartTime
52021 - SmartTime
does not honor False Path on ACM
51939 - SmartTime
Crashes When Creating a Generated Clock Constraint
