Libero IDE v7.0 SP1 Release Notes
(Feb 22, 2006)
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v7.0 Service Pack 1.
Additional Device Support in Libero and Designer Gold.
Libero Gold now supports all family devices through 1 million gates!
The following devices are now available using a new or existing Libero
IDE Gold or Designer Gold license. Devices noted in bold print are added
in this service pack.
- Fusion AFS250, AFS600
- ARM7 CoreMP7 M7A3P250, M7A3P1000
- ARM7 CoreMP7 M7A3PE600
- ProASIC3 A3P060, A3P125, A3P250, A3P400, A3P600, A3P1000
- ProASIC3E A3PE600
- ProASICPLUS APA075, APA150, APA300, APA450, APA600,
APA750, APA1000
- Axcelerator AX125, RTAX250-S, AX500, AX1000, RTAX1000-S
SmartGen Enhancements for Fusion Devices
The SmartGen Fusion Analog System Builder (ASB) now supports:
- Modular configuration of the Fusion analog peripherals. There are 3
options available:
- The default full system, providing use of the ADC Sample Sequence
Controller (ASSC), System Monitor Evaluation (SMEV) phase state machine,
System Monitor Transition (SMTR) phase state machine, and the input
analog multiplexer plus ADC (AB) block
- A subset system, providing use of the ASSC and AB blocks only. Use
this option to process the ADC data directly from the ADC results bus
or the ASSC RAM
- A "no Fusion IP" system, providing use of the AB function
only. Use this option when you want to completely manage the ADC and
all related functionality of the AB block with your own design
- User defined external V
REF
. Fusion provides a default internal V
REF
of 2.56 volts, and now you can choose to supply an external V
REF
up to 3.3 volts.
- User defined digital filtering. Digital filtering is used to smooth
and reduce the input signal noise. You can now experiment with different
values to determine what value works best for the application.
- Internal voltage and temperature monitor functions.
The SmartGen Fusion Memory System Builder now includes an option to protect
the client data from JTAG read/write actions. Initialization, data storage,
and RAM initialization clients can be protected by selecting the option
in the configuration dialog menu.
SmartGen Fusion Analog System and Memory System Builders now provide Verilog
output of the RTL.
SmartGen Analog System and Memory System Builders now include an IP file
version audit. You will be alerted whenever the ASB or NVM IP cores are
in need of update or have updates available. This is determined by the
version of the common file set which may change with each release. When
updates are available it is not mandatory for you to update the core. When
a workspace contains cores using a mixture of the common file sets then
the older cores must be updated.
Fusion UJTAG Support
The UJTAG Macro is now supported. Dynamic CCC/PLL support will be available
in a future release.
New Fusion Device and Package Support
| Device/Die |
Packages |
Speed Grade |
| AFS250 |
208 PQFP |
Std, -1, -2 |
| AFS250 |
256 FBGA |
Std, -1, -2 |
Fusion Synthesis Support
Synthesis for the Fusion AFS250 requires Synplify 8.5b and must be downloaded
directly from Synplicity at http://www.synplicity.com/downloads/download1.html.
Availability from Synplicity is approximately March 1, 2006.
Synplify 8.2g, available in Libero IDE v7.0, supports the AFS600 device.
Fusion Notes
53014 – After installing SP1, existing Fusion AFS600 PLL designs
will be invalidated and automatically set back to Precompiled state. Re-import
the netlist, compile, and rerun layout using "Incremental Fixed On".
User constraints can be preserved by checking "Keep Existing Physical
Constraints" in the "Import Source Files" user interface.
SP1 fixes a problem where the PLL lock is stuck due to a routing error
in the v7.0 release.
52744 – VHDL Non Volatile Memory (NVM) systems created using the
Libero/SmartGen v7.0 Memory System Builder have new IP file names in SP1.
NVM IP systems must be regenerated using SP1. SP1 will generate the system
using the new IP file names, but the original file names will remain showing
in the Libero File Manager Hierarchy window. You should delete these file
names from the project as they are no longer needed, and may cause confusion
if left remaining.
ProASIC3 UJTAG Support
The UJTAG Macro is now supported. UJTAG tiles are directly connected to
the JTAG test access controller, enabling such features such as Dynamic
Clock Conditioning Circuitry (CCC) and Phase Lock Loop (PLL) reconfiguration.
For Dynamic CCC, an embedded shift register accepts an 80-bit command to
dynamically reconfigure all CCC characteristics such as specific dividers,
delay values, divisor values, phase shift, and more. Click HERE to learn
more about Dynamic CCC/PLL reconfiguration. The UJTAG functionality is
available by instantiating the UJTAG macro directly in the source code
of a design.
Programming Support for M7ProASIC3
STAPL program file generation is now available for the M7A3P1000 device.
AX and RTAX-S Quality of Results (QOR) Performance Improvement
SP1 includes enhanced algorithms that improve the place-and-route efficiency
and performance for AX and RTAX-S devices. The Layout Options menu provides
five effort levels for timing-driven layout that have been re-tuned to
provide improved device performance and decreased runtimes, especially
for larger devices.
AX and RTAX-S I/O Support
LVCMOS 2.5v 6mA high slew rate I/O is now available for these devices.
RTAX2000S Package Support
The 256 CQFP is now available for the RTAX2000S. Note: PALACE 3.1 (available
in Libero v7.0) does not support this package. PALACE support for this
package will be available in a future release.
RTAX-S Routing Changes
Designer 7.0-SP1 includes a routing modification which eliminates anomalous
current increases due to space radiation single event upsets (SEU) in the
embedded SRAM FIFO controllers on RTAX-S FPGAs. Designers targeting RTAX-S
should use this software version to avoid the SEU-induced current increases.
For RTAX-S designers who are unable to update the Designer software on
their current project, the SEU-induced current increases can be avoided
by instantiating all available SRAM blocks in the target RTAX-S device
with an unconnected SRAM macro.
Libero IDE v7.0 SP1 requires a current Libero IDE v6.0 or newer license.
General
59133 – Change
in Synplify Bus Naming Causes Failure in Setting GCF & PDC File Constraints
47408 – Using
Upper Case Letters For File Name When Exporting IBIS Model
52633 – After generating a Fusion voltage monitor
function in SmartGen, red question marks show in Libero Project Manager
Design Hierarchy Window SmartGen list associated with the assc.v file.
This question mark is cosmetic only and does not indicate a problem with
the file.
52722 – Imported FlexRAM file for Fusion NVM design
is corrupted. If you create a new Fusion project with Libero 7.0 SP1 and
import a FlexRAM core that was generated using Libero/SmartGen v7.0 into
a Memory System Builder core, you will get an error "Specified core
has been corrupted and needs to be regenerated". You must regenerate
this core after import using SP1.
51573 – SP1 removes the FG256 package option for
the M7A3P250 device. This is not a valid package option for the M7A3P250.
ModelSim
53117 – ModelSim AE simulation iteration
number must be changed to 200 for Verilog Fusion designs. Fusion CAE models
depend on simulation iterations to convert real values to standard logic.
In VHDL implementations the real values are represented by 32-bit vectors.
it takes 64 simulation delta cycles (0 time) to transmit the bit stream
(32 bits of data, 32 bits of "separators"). ModelSim AE
has a default value of 100 iterations, which is adequate for VHDL. In Verilog,
the real values are represented by 64-bit vectors using the "real2bits" Verilog
built-in function. As a result it takes 128 delta cycles to transmit the
bit-stream (64 bits of data, 64 bits of "separators"). The default
value of 100 in ModelSim AE is not sufficient for Verilog designs.
To increase the iteration limit, in ModelSim, select Simulate => Runtime
Options => and select 200.
Libero Flow
53189 – CoreMP7 VHDL Support
Changes have been made in the Post-Synthesis VHDL Export of CoreMP7 Designs.
Previously, a double entity declaration existed of the A7S module (once
in the a7sBFM_TS_a3pe.vhd and again in the VHD file generated by Synplicity),
which caused the following error in ModelSim -
"# ** Error: (vsim-13) Recompile ../simulation/postsynth.YourTopLevelEntity
(def_arch) because ../simulation/postsynth.a7s has changed."
To bind the A7S module to its correct declaration two lines will be added
to the generated VHDL file which direct ModelSim to use the declaration
found in the a7sBFM_TS_a3pe.vhd file, as shown below -
for all : A7S
use entity work.A7S(DEF_ARCH);
Synplify AE
53379 – Synplify 8.2G does not support the Fusion
AFS250 device. If you use Synplify 8.2G (included in the Libero IDE v7.0
release software) for the AFS250, Synplify will map the netlist with the
device set to AFS600. Synthesis support for the AFS250 is available in
Synplify 8.5b, available directly from Synplicity approximately March 1,
2006.
WaveFormer Lite AE
29143 – Support
For Data Type Bit For Clock Signal In WaveFormer Lite
PALACE
53378 – PALACE 3.1 does not support the RTAX2000S
256CQFP package. This package will be supported in a future PALACE release.
SmartGen
51812 – Creating a Fusion Current Monitor with
negative polarity requires selecting the associated voltage peripheral
and setting the input voltage to a negative voltage. In the Current Monitor
dialog, you must check the "Use Voltage" checkbox in order to
enter values into the "Input Voltage" window.
51936 – SmartGen
Uses the Flags of Only One of the Instances in a Cascaded FIFO
51935 – SmartGen
ProASIC3 and Fusion Dynamic CCC Bypass Mode Configuration
51938 – The
Constant Comparator is not working for 6 bits wide configuration
53456 – For Fusion DIVIDED and DELAYED CLOCK macro,
the netlist generated through Smartgen is incorrect when the input clock
source is Internal logic or External I/O. The output of PLLINT is not connected
to CLKDIVDLY; instead CLK is directly given as input to the macro. The
problem occurs for both verilog and vhdl netlists.
Work-around: Instead of driving CLKDIVDLY1 macro directly
by CLK, it should be driven by output of PLLINT (CLKP).
There netlist generated from SmartGen needs to be modified as follows:
The incorrect netlist is as follow:
module CDD_IL(CLK,GL,Y,RESET);
input CLK;
output GL, Y;
input RESET;
wire CLKP, VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
PLLINT pllint1(.A(CLK), .Y(CLKP));
CLKDIVDLY1 Inst1(.CLK(CLK), .RESET(RESET), .GL(GL), .Y(Y),
.ODIV0(GND), .ODIV1(GND), .ODIV2(GND), .ODIV3(GND),
.ODIV4(GND), .ODIVHALF(GND), .DLYY0(GND), .DLYY1(GND),
.DLYY2(GND), .DLYY3(GND), .DLYY4(GND), .DLYGL0(GND),
.DLYGL1(GND), .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND));
endmodule
The corrected netlist is as follows:
module CDD_IL(CLK,GL,Y,RESET);
input CLK;
output GL, Y;
input RESET;
wire CLKP, VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
PLLINT pllint1(.A(CLK), .Y(CLKP));
CLKDIVDLY1 Inst1(.CLK(CLKP) .RESET(RESET), .GL(GL), .Y(Y),
.ODIV0(GND), .ODIV1(GND), .ODIV2(GND), .ODIV3(GND),
.ODIV4(GND), .ODIVHALF(GND), .DLYY0(GND), .DLYY1(GND),
.DLYY2(GND), .DLYY3(GND), .DLYY4(GND), .DLYGL0(GND),
.DLYGL1(GND), .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND));
endmodule
