Libero IDE v6.2 Release Notes
(updated Aug 30, 2005)
Thank you for your interest in Actel's Libero Integrated Development
Environment (IDE) FPGA design and development software. These release
notes outline various updates in the v6.2 software.
Libero
is now available for Solaris and Linux Operating Systems.
Tools include Project Manager, HDL Editor, Synplify AE Synthesis, ModelSim AE
Simulation, PALACE AE Physical Synthesis, and the entire Designer Physical
Implementation tool suite. All devices are supported and floating licenses
are available.
SmartTime
Timing Environment
SmartTime Timing Environment enables you to perform detailed timing
analysis and quickly determine the steps necessary to achieve design
closure. The SmartTime environment incorporates multiple "views" as
follows:
- The SmartTime Constraints Editor view enables you to list, edit and
create precise timing constraints. It includes a graphical user interface
with visual dialogs that help you meet your timing requirements.
- The SmartTime Analyzer view simplifies the analysis process by enabling
you to track paths with timing violations and identify critical paths.
You can then set specific timing constraints or exceptions on the violating
paths to tighten or relax the requirements and quickly iterate toward
timing closure.
- The SmartTime Timing Analyzer view enables you to manage multiple
clock domains, perform timing analysis and identify timing violations
across synchronous or asynchronous clock domains.
- SmartTime also supports the SDC (Synopsys Design Constraints) flow.
To learn more, read the SmartTime
Tutorial.
- SmartTime includes detailed and user-customizable timing reports.
- SmartTime supports ProASIC3, ProASIC3E, ProASICPLUS, ProASIC,
SX-A, RTAX, RTAX-S, and eX devices.
Libero
IDE Enhancements
IDE Project Manager
- Now supports Verilog 2001 standards (See Important
Notices below)
- Now includes an enhanced Constraints Management interface whereby
all constraints are identified and presented. Constraints, including
SDC, can be individually selected and prioritized for passing to Designer
for physical implementation. SDC constraints are passed to the SmartTime
constraints editor for use in timing analysis and closure.
- "Find Next" command is now available in the "Find
Module" dialog box.
- In the Design Flow Window, you can now bypass synthesis and pass
the source files directly to Designer (structural flow only).
- "Tool Profiles" now automatically finds compatible tools
(Synplify, ModelSim, WaveFormer Lite, Precision, etc) and reports
the version number for easier selection into the project. Profiles
can also be exported for use in other versions of Libero.
MultiView Navigator
- Provides cross-probing between SmartTime and ChipPlanner. After place-and-route
you can select a critical path in SmartTime and observe the logic path
and direction of the signal path in ChipPlanner. This feature makes
it easy to select a path and identify the relative location of the
logic that makes up the path.
- Includes a new "Package Pins Tab" in the I/O Attribute
editor that lists all pins in a targeted package, along with the I/O
attributes and I/O banks. This makes it easier to assign address/data
ports to adjacent pins and assign or view Vref pins.
- Includes Active Lists. You can now compile customized lists of important
resources such as nets, macros, regions, and instances. Lists are updated
dynamically when the design objects' state changes. This feature makes
it very easy to track resources and floorplan the design.
ACTgen Core Generator
- RAM Enhancements for Axcelerator supports full RAM cascading, including
variable aspect data widths. Variable aspect ratios, enabled for 2
port and dual port RAMs, plus depth and width cascading is provided.
- New RAM initialization for ProASIC3 and Axcelerator devices. This
memory editor provides an intuitive way of specifying the memory content
during the design phase instead of the simulation stage, reducing the
simulation cycle time. This is especially useful in the case of variable
aspect ratio RAMs.
ProASIC3 Specific Enhancements
- A new automatic "Local Clock Assignment" (LCA) feature
detects if there are more than 6 global nets coming from the user netlist
or PDC constraints and if so, automatically assigns the global nets
to either chip or quadrant regions.
- A high effort Timing-Driven Place-and-Route flow can improve device
performance 7% (average) however there will be a significant run time
increase. A small percentage performance improvement may take several
hours, depending on the device size and complexity.
- An enhanced incremental router flow preserves previous routing and
allows a true ECO mode when recompiling, importing an ECO netlist,
or making minor modifications in global assignments and regions.
- Design specific IBIS models can now be exported after place-and-route.
The generated IBIS file includes package, package pin numbers, signal
names, and I/O models.
- New "Global Routing" techniques significantly reduce routing
run times, especially in large devices.
ProASICPLUS and 500k Routability Enhancements
- A new routing algorithm improves the routability of congested designs.
Previously un-routable designs may succeed by using a lower Timing
Weight selection. Performance may degrade in some cases.
SmartPower
- I/O standard dependent intrinsic power model for Outbuf/Tribuf/Bibuf
macros for the AX/RTAX-S families. This new feature allows more accurate
modeling of power consumption.
New
OEM Tool Releases
Synplicity Synplify AE 8.1a Synthesis software includes:
- RAM inference for ProASICPLUS devices
- Synopsys Design Constraints (SDC) generation and export
- 7% (average) Performance Improvement for Axcelerator devices via
critical path re-synthesis
- I/O pad selection for ProASICPLUS devices
Magma Design Automation PALACE AE 3.0 Physical Synthesis software now
supports performance optimization for Axcelerator devices. An additional
15% (average) performance improvement can be realized on most designs.
SynaptiCad WaveFormer Lite AE 10.04A Testbench generation software includes
support for USB dongle hardware keys for node locked licenses, and bug
fixes.
Mentor Graphics ModelSim AE 6.0c_P1 Simulation Software is included
in Actel's FREE Libero Gold edition.
Mentor Graphics/Actel ViewDraw AE 6.2 Schematic Capture Software
New
Package Support
Axcelerator Packages
- AX1000 624 LGA
- AX2000 624 LGA
- AX2000 1152 LGA
- RTAX1000S 624 LGA
- RTAX2000S 624 LGA
- RTAX2000S 1152 LGA
SX-S Packages
- SX32A 84 CQFP
- RTSX32S 84 CQFP
- RTSX72S 624 LGA
ProASICPLUS Packages
- APA600 624 LGA
- APA1000 624 LGA
- APA1000 1152 LGA
The new Verilog 2001 keywords are as follows:
automatic
cell
config
design
endconfig
endgenerate
generate
genvar
instance
liblist
localparam
noshowcancelled
pulsestyle_onevent
pulsestyle_ondetect
showcancelled
use
46690 - New ProASIC3/E I/O specifications.
The ProASIC3/E datasheet has been modified with new I/O limitations as
follows:
- For A3P250 and A3P400 devices, the maximum number of LVPECL pairs
in the east and west banks cannot exceed 15. Refer to package pin list
in the datasheet for position assignments of the 15 LVPECL pairs. A3P400
will be available in a future software release.
46661 - SmartTime Constraints Editor
checks imported SDC file for errors. If any errors are found,
SmartTime generates an error. You must manually correct the error and
re-import the file into SmartTime. This is a different behavior from
previous SDC import where error checking is done later in the flow.
43901 - DCF support for AX devices will
be obsolete after v6.2. Designer Constraint Format (DCF),
historically used by Timer for timing constraints, will not be supported
in subsequent releases. Customers should convert DCF files to SDC.
After v6.2, Libero/Designer will not import or export DCF files.
Operating System Final Support
This release is the final support for:
Libero IDE v6.2 requires a current Libero v6.0 license.
Libero IDE Gold is now Actel's FREE development software. Libero Gold
includes all tools EXCEPT WaveFormer Lite ReactiveTestbench/VCD Import
and PALACE. Libero Gold supports Actel devices through 300k gates plus
the A3P400 and A3P600E devices.
45 day Free Evaluation Licenses, supporting all devices, are also available
but do not support device programming.
Libero IDE Platinum is available for purchase at Actel authorized distributors
or sales offices.
Check out the software editions and
license charts for descriptions
of the tools and available licenses. To register for your FREE license, go to
the Software Licenses and Registration System.
ViewDraw
40714 - ViewDraw AE no longer requires certain registry
and environment variables to be set before the Viewdraw.exe is called
from Libero.exe. The configurator.exe no longer modifies the PATH or
ACTELWDIR. Also, it will not modify as many registry entries. The configurator.exe
is now located at \bin\configurator.exe rather than at \configurator.exe.
This is to better ensure that dependencies on runtime DLLs are localized
to the folder that contains the executable.
Synthesis
46940 - 47360 - 46320 - Synplify
does not use "renamed object names" in SDC in VHDL designs
(APA, A3P/E, AX)
44345 - Can
not launch Synplify or Designer from Design Flow Window if an EDIF
netlist is imported after project is created (all devices)
44153 - LeonardoSpectrum 2003a is not fully supported
in Libero v6.2. Using 2003a, when LeonardoSpectrum is selected for Synthesis,
the Design Flow Window icon will not turn green because Libero does not
detect if synthesis succeeded. The netlist will be detected by Libero
and the flow is not affected.
44751 - SDC from Synplicity for 500k devices will not
drive Timing Driven Place-and-Route. In v6.2 Libero automatically passes
the Synplify generated SDC to Designer. The SDC is generated for 500k
devices and then passed automatically but is not used for TDPR. It can
be used for Timing analysis. In order to drive TDPR, an equivalent GCF
constraint must be written.
46546 - Improper
PLL Macro placement (A3P/A3PE)
48080 - Synplify AE default supports Verilog 1995.
Libero 6.2 does not hard code any Verilog standards in the Synplify *syn.prj
file, but users who include Verilog 2001 standards in their Verilog source
code will have to enable Verilog 2001 standards within the Synpllify
user interface as follows: Options => Configure Verilog Compiler => Select/enable
Verilog 2001.
Simulation
44218 - Asynchronous
Read and Asynchronous Write to the same address
PALACE
46941 - The "Keep_Device" command does not
necessarily keep the design from being promoted to a larger device if
the device utilization is high. During the optimization process, if a
device is very full, PALACE attempts to stay within the targeted device
using "Keep_Device", however this does not guarantee that promotion
to a larger device will not occur.
46942 - PALACE 3.0 uses "STD" speed grade
for all families. Prior to 3.0, PALACE by default would use -2 speed
grade. Better performance may be realized from PALACE by selecting -2
speed grade. To do so, in the PALACE Tool Profile ' Edit Profile ' Additional
Parameters window and adding "- speed -2".
47414 - Libero IDE v6.2 automatically shows the version
number for a tool in the Tool Profile Edit Window, however the PALACE
version number (3.0) is not shown. The version number appears in the
Log File.
ACTgen
46305 - PLL External Feedback is not available. In
v6.2, EXTFB is grayed out and therefore unavailable in the PLL configuration
user interface. EXTFB was available in Libero/Designer v6.1 but is temporarily
disabled. This feature will be available in a future release. (A3P/E)
45617 - ACTgen
hangs when RAM with Max depth/width is being generated (A3P/E)
46618 - Mentor Graphics DX Designer support in ACTgen
is discontinued. ACTgen symbol generation is no longer compatible with
recent versions of DX Designer.
44172 - PLL
clock alignment based on output divider value (APA)
Multiview Navigator
46787 - Unable
to create single (T or B) spine (APA)
46452 - "Configure
Current Active List" command changed to "Edit Current Active
List" (all supported devices)
45833 - Resizing
window should resize the schematic to fit within window (all supported
devices)
45596 - Cell
name is missing from the I/O Properties dialog box (all supported devices)
39845 - Tooltip
and status bar shows wrong I/O options for I/O bank (ProASIC3)
Timer
46509 - Ambiguity
in the clock network (all products)
SmartTime
47029 - Constraints
differ before/after saving and reopening Constraints editor (eX, RTSX-S,
SX-A)
47028 - Constraint
is duplicated when "Keep Existing Constraint" is on (all
supported devices)
46712 - Adding "input
delay - min only" removes in-reg paths for port in max delay analysis
view (all supported devices)
46928 - Occasional
crash when undoing deletion of input delay constraint (all supported
devices)
46643 - Crash
when turnoff inter-domain option after selecting inter-domain set (all
supported devices)
47146 - Loopback
in bibufs option does not work (ProASICPLUS, SX-A)
Designer Other
44013 - Layout
and compile are invalidated during prototyping flow (Axcelerator and
RTAX-S)
45031 - Pin
assignment command in Pin Edit does not work with "no fix" option
(SX-A)
47409 - Exporting IBIS file will error out if the file
name contains upper-case characters. Ensure that the file name does not
contain upper-case characters. (ProASIC3/E)
30859 - Post-combiner device utilization is confusing
47296 - Re-compile
flow may require re-import (ProASIC3/E)
47246 - Layout
detects false combinational loop (SX-A, eX, RTSX-S, ProASIC, ProASICPLUS)
47474 - Need
to regenerate PLL to have new properties (ProASIC3/E)
Solaris and Linux Specific Known Issues
47418 - Environment Variables set up for PALACE. Use
of PALACE within Libero Solaris/Linux requires setting up the Environment
Variables prior to invoking Libero and PALACE. Set environment variables
as follows: Setenv PALACE_ROOT <palace_install_dir&gr;
Set path ($PALACE_ROOT/bin $path)
47466 - Tooltips not visible. When pointing to various
tools, icons, or files in the Libero interface Tooltip information may
partially or not visible. Tooltip information can be viewed in the Status
Bar location.
47667 - PALACE AE 3.0 is not supported on RedHat Linux
9. Supported Linux versions are RH Linux 8 and HREL 3. PALACE will not
run on RH Linux 9. See the System
Requirements page for more information.
47855 - Synplify AE 8.1 is not supported on RedHat
Linux 9. Supported Linux versions are RH Linux 8 and RHEL 3. See the System
Requirements page for more information.
47679 - Simulation library mapping is case sensitive.
Some simulation library names within Libero are provided with upper case
file names. Unix requires lower case. In these cases the libraries will
not be mapped correctly and the library will not be available in ModelSim.
(AX devices only)
Workaround:
- Use the Libero Project Manager Options => Project Settings. Select
the Simulation Tab and browse to point to an existing library.
- Modify the mapping directly within ModelSim
Do not modify the modelsim.ini file as this file will be overwritten
each time ModelSim is invoked.
47555 - Unable to open .PDF reference documents and
User Guides. When selecting a reference manual or User Guide from the
Libero Project Manager Help =&gp; Reference Manuals menu, the selected
document may not open. You must have Acrobat Reader version 5 or newer
to view Actel PDF documents. Acrobat Reader v5 is available from the
Libero Solaris/Linux CD. For Linux users, typically the default PDF reader
is XPDF, which is typically found in /usr/bin/xpdf. Users can then set
File => Preferences => PDF Reader to /usr/bin/xpdf to open Libero
v6.2 documents.
47858 - Inappropriate Tool Profiles message at initial
Libero start up. Libero Project Manager contains a Tool Profiles option
that maintains the OEM tool selection based on project setup settings.
After installation of Libero Solaris or Linux, the initial start up will
show a message "You are running Libero v6.2 for the first time.
Do you want to copy your tool profiles from a previous version of Libero?" This
message can be ignored for first-time use of Libero Solaris or Linux
as there will not be existing tool profiles.
47859 - Tool Profiles selections can only be saved
by a System Administrator. Libero Project Manager contains a Tool Profiles
feature that maintains an OEM tool selection based on project setup settings.
Normally, the tool profile selections would be saved upon exit from the
program. For Libero Solaris/Linux v6.2, Tool Profiles can be setup or
changed, but saving the selected Tool Profiles can only be accomplished
by a user with System Admin rights.
46240 - Recommended
Font size settings for optimal viewing.
47561 – Resizing the Project Settings menu box hides
settings components. In Linux, if you open the Project Settings dialog
box and select the 'Simulation' tab, the size of this dialog box is oversized.
If you try to resize it, some of the settings components will be hidden.
