Libero IDE v6.1 Release Notes
(updated Apr 1, 2005)
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v6.1. These release notes outline various updates for the v6.1
software.
ProASIC3
Support 
This release introduces initial support for Actel's new low cost ProASIC3
(A3P) and ProASIC3 (A3PE) Flash Family devices. Libero IDE v6.1 provides
full design flow support as follows:
- ViewDraw AE schematic capture
- Synplify Synthesis AE optimized performance and utilization
- ModelSim AE and WaveFormer Lite
- ACTgen core support for ProASIC3 features:
- Clock Conditioning Capability (CCC) and PLL definitions via a Visual
PLL Core Generator Wizard
- Dual-Port RAM and FIFO configurations
- 1kbit user Flash ROM (FROM)
- FROM Simulation Flow
- PALACE Physical Synthesis performance optimization
- Import and use of PDC (Physical Design Constraints) and SDC (Synopsys
Design Constraints)
- Multiple Compile options:
- combine registers with I/Os
- superior global spines management
- automatic global promotion
- local clock maximum shared instances
- local clock buffer fan out selection
- Enhanced Compile Reporting
- MultiView Navigator enhancements
- I/O Attribute Editor supports the wide range of I/O choices in
ProASIC3
- Create Quadrant and Local Clock regions with ChipPlanner
- Efficient timing-driven place-and-route process
- Timer support for SDC constraints and pre/post-timing analysis
- New back-annotation timing flow
- Post layout power analysis
Note: Libero IDE/Designer v6.1 does not support
program file generation or device programming for ProASIC3 or ProASIC3E.
ProASIC3 devices and packages supported in Libero v6.1
| Device |
Package |
Speed |
Voltage |
Temp Rng |
Silver |
Gold |
Platinum |
| A3P060 |
100 VQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P060 |
100 VQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P060 |
144 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P060 |
144 FBGA |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P060 |
144 TQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P060 |
144 TQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P125 |
100 VQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P125 |
100 VQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P125 |
144 TQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P125 |
144 TQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P125 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P125 |
208 PQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P250 |
100 VQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P250 |
100 VQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P250 |
144 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P250 |
144 FBGA |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P250 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P250 |
208 PQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P250 |
256 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P250 |
256 FBGA |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P400 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P400 |
208 PQFP |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P400 |
256 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P400 |
256 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P400 |
484 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P400 |
484 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P600 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P600 |
208 PQFP |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P600 |
256 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P600 |
256 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P600 |
484 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P600 |
484 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P1000 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P1000 |
208 PQFP |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P1000 |
256 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P1000 |
256 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
| A3P1000 |
484 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3P1000 |
484 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
ProASIC3E devices and packages supported in Libero v6.1
| Device |
Package |
Speed |
Voltage |
Temp Rng |
Silver |
Gold |
Platinum |
| A3PE600 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3PE600 |
208 PQFP |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3PE600 |
256 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3PE600 |
256 FBGA |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3PE600 |
484 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3PE600 |
484 FBGA |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3PE1500 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3PE1500 |
208 PQFP |
-F |
1.5 |
Com |
N |
N |
Y |
| A3PE3000 |
208 PQFP |
STD, -1, -2 |
1.5 |
Com, Ind |
N |
N |
Y |
| A3PE3000 |
208 PQFP |
-F |
1.5 |
Com |
N |
N |
Y |
Supporting information for ProASIC3
- Libero IDE v6.1
Quickstart Guide
- Application Notes
- ProASIC3 FlashROM (FROM)
- ProASIC3 SRAM/FIFO Blocks
- Using DDR for ProASIC3 Devices
- Using ProASIC3 Clock Conditioning Circuitry
- Using Global Resources in ProASIC3
- ProASIC3 RAM/FIFO Design
- Using ProASIC3 Security Options
- Implementing Multipliers in PA3 using RAM
- ISP for PA3 using FlashPro3
OEM
Tools
- Synplify AE 7.7.1 Synthesis
Synplify AE 7.7.1b introduces full synthesis support for the new ProASIC3
families.
- Waveformer Lite 9.9 Test-Bench
For Libero IDE Platinum (and Eval) users, SynaptiCad's Waveformer Lite
AE contains a new Reactive Test Bench (RTB) and VCD import functions.
- Reactive Test Bench: The Reactive
Test Bench Generation enables you to describe single timing diagram
test benches that react to the your HDL design files and generate
pass/fail reports. With "Reactive Test Bench Generation",
you have the option of drawing "expected" waveforms on
the MUT (Model Under Test) output ports and adding "samples" to
the waveforms to test for specific cases. During simulation, the
code generated by the samples watches the output from the model
under test and compares it to drawn states. The samples can perform
a variety of functions, such as pausing the simulation to debug
a problem, reporting errors and warnings, user-defined actions,
and triggering other samples. View the RTB
tutorial for detailed information.
- VCD File Support: VCD files are
stimulus files that are produced by Verilog simulators. The new
Libero IDE v6.1 Platinum can read in VCD waveforms from previous
simulations and use this data as the starting point for a reactive
test bench.
- ModelSim 5.8d Simulation
New features added to 5.8d (view complete release notes in the ModelSim User
Interface Help Menu for more information)
- The new modelsim.ini variable CheckPlusargs in
the [vsim] section controls checking of plusargs on the vsim command
line.
- The Wave window has a new keyboard shortcut 's'
to bring into view and center the currently active cursor in the
window.
- The Dataflow window can now be used for HDL regions
of mixed SystemC designs.
- The coverage save instance command normally saves
the specifiedinstance and all instances below it, recursively.
A norecursiveoption has been added to limit the save to only one
level.
- PALACE 2.0 Physical Synthesis
PALACE 2.0 introduces full support for Actel's new ProASIC3 and ProASIC3E
families, in addition to ProASICPLUS. Adding PALACE v2.0
into the design flow will deliver a performance improvement of one
additional speed grade for most designs.
- FlashPro 3.2 (Same as Libero IDE v6.0)
- Silicon Explorer v5.0 SP2 (Same as Libero IDE v6.0)
- ChainBuilder v1.0 (Same as Libero IDE v6.0)
Optional
Software
- Mentor Graphics Synthesis support for PROASIC3
Synthesis support for ProASIC3 is provided by Mentor Graphics as
follows:
- Synplify Pro AE 7.7.1 Synthesis
Synplify Pro AE 7.7.1b introduces full synthesis support for the new
ProASIC3 family devices.
Requirements for ProASIC and ProASICPLUS Users
All ProASIC and ProASICPLUS customers are required to upgrade
their existing designs to Libero/Designer version 6.1. Important place-and-route
software changes have been made that must be factored into your design
to ensure proper handling of all conditions.
Windows NT Support
2005 is the last year Libero and Designer will be supported on Windows
NT.
GCF Timing Support
GCF Timing Constraint support for ProASICPlus (APA) family is being
obsoleted. Libero and Designer v6.1 (and service packs) will be the last
version supporting GCF to SDC conversion of the following GCF timing
constraints for APA devices. Subsequent releases of Libero and Designer
will not recognize these constraints. For any APA design-in-process that
is expected to be run on releases following v6.1, customers should take
care now to remove these GCF timing constraints from their GCF files
and substitute them with an equivalent SDC constraint file (exported
automatically by Designer after a GCF import or manually through Designer
interface).
The GCF constraints being obsoleted are shown below, along with the
corresponding SDC.
| GCF Constraint |
SDC Constraint |
| create_clock -period <period_value> portname |
create_clock -period period_value portname |
| create_clock -period <period_value> netname |
create_clock -period period_value potential_clock_port_pin_name |
| set_false_path [-from from_port][-through any_port][-to to_port] |
set_false_path -through through_list |
| set_input_to_register_delay <delay> [-from inp_port] |
set_max_delay delay_value [-from from_list][-to to_list] |
| set_multicycle_path <num_cycles> -from reg_port [-through_any_port]
[-to_port] |
set_multicycle_path path_multiplier [-from from_list][-to to_list] |
| set_register_to_output_delay <delay> -to out_port |
set_max_delay delay_value [-from from_list][-to to_list] |
| set_max_delay -from first_pin_in_the_list -to last_pin_in_the_list |
set_max_delay delay_value [-from from_list][-to to_list] |
Libero IDE v6.1 requires a current Libero IDE v6.0 license. No license
upgrade is required.
39868 - Un-install any previous Libero IDE 6.1 EAP
version
39843/39844 - Previously created ProASIC3 or ProASIC3E
ADB files are not usable. Any previously created ProASIC3/E design using
pre-production software is not compatible with v6.1 and must be re-created
using v6.1. Do not use an ADB file generated by pre-v6.1 production software
(EAP, Test, FAE).
STAPL (Programming) file generation is NOT supported
in Libero/Designer v6.1 for ProASIC3 or ProASIC3E. All other families
are supported.
39863 - Minibanks for ProASIC3 or ProASIC3E are not
supported. Minbanks, as referenced in the ProASIC3 or ProASIC3E datasheet,
are not supported in v6.1
39816/42903 - ProASIC3 I/O GTLP software values exceed
datasheet values. In v6.1 software:
- gtlp25_vol_5x datasheet value is 33mA and the software limit is 40
mA
- gtlp33_vol_5x datasheet value is 35mA and the software limit is 51
mA
Both meet the GTLP industry specification of minimum 24mA.
FlashPro: Only FlashPro 3.2 (or earlier) can be used
with Libero/Designer v6.1
ACTgen
37006 - 43541 - ACTgen
generates wrong netlist for pipelined barrel shifter (ProASIC3, ProASIC3E,
and AX devices)
35109 - When EDAC macros are imported from one workspace
to another, the EDAC IP macros edaci_* are not copied into the workspace.
The user must regenerate the EDAC macro to be included in the workspace.
(AX family)
37021 - 40950 - 43546 - ACTgen
does not allow variable aspect ratios for dual port RAM (ProASIC3,
ProASIC3E, and AX devices)
41196 - 37242 RAM
blockage usage issue (ProASIC3 and ProASIC3E devices)
41198 - 37072 FIFO
controller issue (ProASIC3 and ProASIC3E devices)
Designer
25695 - Power
values are not dynamically updated when output load changed (ProASICPLUS and
ProASIC3E devices)
34331 - Placement
fails due to IO + Region constraints not snapping (ProASICPLUS and
ProASIC3E devices)
38402 - Clock
placer puts clocks in regions with insufficient I/O resources (ProASIC3E
and AX devices)
42854 - Designer
crashes when compile option - demote global nets is turned on (ProASIC3
and ProASIC3E devices)
43069 - Designer
crashes when compile option - demote global nets is turned on for very
low fanout nets (ProASICPLUS and ProASIC3E devices)
Multiview Navigator
36690 - Resource
Count provided by Prelayout checker is incorrect when Regions intersect
39890 - Region
snapping is not functioning correctly when crossing boundaries
Timer
39994 - Exported
SDC Constraints on Enabled Flip-Flops Do Not Match the Netlist (ProASICPLUS and
ProASIC3E devices)
40052 - Warning
Message Appears When a Combined Register Has a Constraint (ProASICPLUS and
ProASIC3E devices)
41266 - TDPR
cannot use constraint set (SXA devices)
42752 - Missing
path in timing report from input to WRB ram pin (ProASIC3, APA, AX,
SXA devices)
Synplify
37120 - Synplify
Not Using Global For Set/Reset (ProASIC3 and ProASIC3E devices)
42747 - Synplify
Inferring CLKINT In Front Of Special CLKBUFs (APA and ProASIC3E devices)
ViewDraw
39643/15199 - Bus
Renaming In ViewDraw (All devices)
40342 - Embedded
Images in ViewDraw Schematics (All devices)
40618 - ViewDraw
fails to start on various PCs (All devices)
41706 - Failed
to push into symbol (All devices)
PALACE
41448 - PALACE
must have physical effort set to effort 1 on designs that have multi-technology
I/Os (ProASIC3E devices)
