Libero IDE v6.0 Release Notes
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v6.0. These release notes outline new features and benefits, new
device support, known limitations, and other detailed information about
this release.
Synplicity Synplify
Synplify AE 7.5.1a contains critical path re-synthesis
for ProASICPLUS family devices. Critical path re-synthesis
increases the performance of the device.
Synplify AE 7.5.1a is now available for Silver, Gold,
and Platinum Users. Synplify Lite is now eliminated, offering the same
Synplify AE synthesis features to all Libero users. Silver and Gold users
now have the following features not previously available in Synplify Lite:
- SCOPE multi-level design constraints manager/editor, provides complete
control over the synthesis process
- Interface to Synplify Pro's HDL Analyst, allows Synplify AE to pass
design information to HDL Analyst. Helps identify critical paths.
- Hierarchical Netlist (previously was flattened netlist)
- Hierarchical Browser
- TCL Scripting input
Synplify Pro AE is Synplicity's full-featured synthesis
tool. An Actel Edition (AE) of Synplify Pro is automatically installed
with the Libero IDE installation (unless you have elected to not install
it). Synplify Pro AE 7.5.1a features, in addition to Synplify AE are:
- MultiPoint™ Synthesis provides superior incremental design methodology
- HDL Analyst® Solution generates an RTL block diagram from HDL
code, and helps identify critical paths
- FSM Explorer automatically finds and selects the best coding style
option for the fastest performance
- Probe Point Creation allows any signal to be tied to an external pin
for testing without HDL code changes
- Generic cross-Probing of Critical Paths cross-probes between HDL Analysis
and 3rd party timing reports
- Re-timing/automatic register balancing across combinatorial logic
to increase performance
Synplify Pro AE requires a separate license in addition to Libero IDE
or Designer. Contact your local Actel Sales office or Distributor for pricing
information.
WaveFormer Lite AE 9.6* - Libero Platinum users have
access to 2 new features:
- Reactive Test Bench (RTB) enables building a testbench model to which
the simulation results can be compared, reducing design verification
time.
- Verilog Change Dump (VCD) allows import of IEEE 1364 standard waveforms
into the testbench.
* Part of WaveFormer Lite AE 9.6. Available as download from Actel late
June
Magma PALACE AE 1.2 is now available as part of Libero
Platinum, at no extra cost; includes support for Synopsys Design Constraint
(SDC) flow in Libero IDE. Industry standard file format (SDC) ensures compatibility
and seamless efficient flow through PALACE, Timer, and Place/Route process.
Project Manager
Implementations of a Design - "Implementations"
allows creation, edit, and saving of multiple views or variations of a
design within the project. You must have an ADB, backannotated or programming/debugging
files, or a post-layout simulation folder. This enables the user to test
variations of a design to achieve an optimal solution.
File Structure Layout - More descriptive and better
organized file structure layout in the File Manager window, visually showing
a more intuitive relationship of the files, and easier access to each.
Makes the design process less confusing and more efficient.
PALACE Physical Synthesis - PALACE Physical Synthesis
for ProASICPLUS family devices is fully integrated into
the Libero IDE Project Manager, streamlining the entire flow. PALACE can
be launched and managed with new user interfaces. All PALACE files are
managed directly by Libero. Bring PALACE into the design flow by clicking
the new "Configure Design Flow"
button in the Libero Design Flow Window.
New Device Support
- A42MX36, A54SX72A, and RTSX72S devices are now supported in Silver
and Gold Editions
- AX1000 in CG624 package
- AX250 in CQ208 and CQ352 packages
- RTAX250S in CQ352 and CQ208 packages
ACTgen
Selecting and configuring an ACTgen core is significantly easier through
a redesigned user interface. New functions include:
- Find a specific core by scanning and selecting from
- an alphabetized list of categories (arithmetic, comparators, counters,)
- an alphabetized list of all macro functions for your device
- View
- only cores associated with a family
- all cores within a category
- all cores in a functional type
- the version of a core
- brief description of any core
- a "Configured Core View" workspace that shows all cores
selected and configured for the project
MultiView Navigator
The MVN supports new features enhancing overall usability.
Logical Cones - Logical cones enable you to view, highlight,
and cross-probe a selected subset of your netlist. Use this when iterating
timing closure for better visibility into your design.
Active Message System (AMS) - AMS gives you immediate
feedback on the last action performed in hierarchical order.
Prelayout Checker - An improved Prelayout Checker detects
constraint errors earlier in the design flow.
Include RAM and I/O in Spine and Net Regions Feature (ProASIC,
ProASICPLUS Families) - This option affects
the behavior of 1) the use_global constraint, 2) the set_net_region constraint,
and 3) the creation of spines in the MultiView Navigator.
- Selecting "Include RAM and I/O in Spine and Net Regions"
from the Compile Option enables you to assign memory and I/O to spine
(LocalClock) and net regions. When this option is checked, Designer
will apply the use_global and set_net_region constraints to core cells,
memory, and I/O. When unchecked, Designer applies the use_global and
set_net_region constraints to core cells only. For new designs, this
box is automatically checked. If a design created using Libero or Designer
v5.2 SP1 or earlier is opened with v6.0, this Compile Option is unchecked
by default. If you change this default setting, you must recompile
your design.
- This option also determines whether memory and I/O are included in
a LocalClock region that you create with the ChipPlanner tool. If checked,
memory and I/O are included. If not checked, they are excluded.
Other MVN Ease of Use Improvements
- Each logical instance in the Hierarchy Window and the Find Results
tabs have a Properties option from which you can copy an instance name
and location.
- The Properties dialog box now shows the Location, Region Constraint,
Cell Name, and Netlist properties of the logical instance.
- Drivers of nets are now shown in the Nets tab in the Hierarchy Window
of the MVN.
- You may control the color of individual regions for enhanced visibility.
Timer / Timing Engine
The Timer tool has the following new features:
- Importing SDC (Synopsys Design Constraints) as a source file
- Both the netlist and timing constraints (SDC File) can be imported
at the same time in a pre-compiled state
- Designer audits the SDC file and can detect any changes or updates
made to the original file. This feature helps in passing SDC files
created by third party tools.
- Improved constraints flow for ProASICPLUS family devices through improved
pin name mapping; SDC constraints entered in the Timer user interface
(using SDC import or generated within Designer) are mapped to original
netlist names, saved correctly in the database, and correctly exported
to third-party tools.
- Timer
- Clock frequency estimation accounts for Duty Cycle. The value specified
in the clock constraint for the duty cycle is now taken into account
in the clock frequency. When the user enters a clock constraint in
the Timer GUI, the frequency estimated by Timer is discarded, and
the max frequency now appears in the summary tab with the duty cycle
taken into account.
ProASICPLUS Performance
ProASICPLUS family device performance has been improved
10% on average via improvements in Timing Driven Place
& Route (TDPR), improved routing algorithms, and congestion relief.
Up to 40% improvement has been seen in some complex designs, and previously
un-routable designs are now routing with v6.0.
For existing users, Libero IDE v6.0 requires a license upgrade. Customers
with current paid licenses will automatically receive an updated license.
Please carefully follow the instructions in the update license email to
install your license properly.
Libero IDE v6.0 contains the following:
- Actel Designer v6.0
- Synplicity Synplify AE 7.5.1a
- Synplicity Synplify Pro AE 7.5.1a (note 1)
- Mentor Graphics ModelSim AE 5.8b
- SynaptiCad WaveFormer Lite AE 9.0 (note 2)
- Mentor Graphics ViewDraw AE 7.7
- Magma PALACE AE 1.2
- Actel ChainBuilder v1.0
- Actel FlashPro v3.2
- Actel Silicon Explorer II v5.0 SP2
Note 1: Synplify Pro AE requires purchase of a stand-alone license, available
from Actel.
Note 2: WaveFormer Lite 9.6 will be available as a web download by June
30. WaveFormer Lite 9.6 contains 2 new features available in to Libero
Platinum users only. See WaveFormer Lite AE 9.6 New Features below.
Click any of the listed issues for a description and workaround.
Libero Known Issues
Synplify
32251 - Synplify
deletes the existing *.srr (log) file during the opening of project file
PALACE
38281 - Set_false_path
-through constraint is ignored in PALACE
36059 - Co-installation
of multiple PALACE versions
35123 - Support
for set_memory_region constraint
Project Manager
37815 - Designer
state is not reset when a new implementation is created
38474 - Synplify
uses default die and package selection
34254 - Opening
*.adb from "Run Designer" does not trigger an audit start
Miscellaneous: Opening PDF Reference Documents
37928 - An error message may appear when opening the libero_manuals.pdf
file, similar to "Opening an Acrobat document created in a newer version
of Acrobat. All features may not be enabled in Acrobat 5.0." Libero
reference manuals are created in Acrobat 6.0, and Acrobat by default encourages
users to use 6.0. Actel recommends that you upgrade to Acrobat Reader 6.0.
No features are disabled if you open the PDF files in Acrobat Reader or
Acrobat 5.0.
Designer Known Issues
ACTgen
32591
- ACTgen implements delay parameter incorrectly
37193 - ACTgen
cannot generate output buffers, bi-directional buffers, or tri-state
buffers for Axcelerator devices
36231 - Core
regeneration fails if the log file is read-only
38309 - Cannot
import GEN file into Libero
Place-and-Route
38191, 32033
- The dont_optimize or dont_touch GCF constraints are not recognized
after layout
36298,
36886 - Layout fails for duplicate net names in the netlist
37632,
35168, 36527 - Multi-tile core cells and spine constraints
37664,
37386 - Layout is invalidated if MVN is open and you click Layout
Timer
31795 - Fanout
display in Timer does not match the display in MultiView Navigator
32342 - Hold
check analysis does not support multi-cycle constraints
33574 - Multi-cycle
path constraints are not taken into account for clock frequency calculation
35515 - Error
messages when using unsupported constraints
36793 - Constraints
entered through SDC do not appear in Timer
37232 - Some
timing constraints are not being honored by Layout
38104 - Invalid
use of the wildcard symbol for bus signal
MultiView Navigator
33978 - Layout
fails when assigning <net>_BUF_AUTO macros to a user-defined region
37071 - If Local
Clock Region cannot be created due to insufficient resource, macros will
still be left unplaced
37228 - "Assertion
Failed" error occurs when moving or resizing exclusive region with
fixed logic in the region
37233 -Exported
PDC with exclusive regions cannot be imported and re-compiled by Designer
Programming Files
38282 - Axcelerator: AFM files generated from v6.0 must use Sculptor 4.44.0
for programming
