Actel

Libero IDE v5.0 Service Pack 1 Release Notes

Thank you for your interest in Actel's Libero Integrated Design Environment (IDE) v5.0 Service Pack 1. These SP1 release notes outline new features and benefits, new device support, known limitations, and other information about this release.

Included Software

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Libero IDE v5.0/Designer v5.0 SP1

New Features and Enhancements

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There are no new features in Libero IDE v5.0 SP1. This release addresses known bugs and issues only.

NOTICE: V5.0 SP1 WILL BE THE LAST RELEASE SUPPORTING WINDOWS 98

Resolved Issues

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Designer Resolved Issues

The following issues have been resolved.

ChipPlanner

27864 - Changing the target device after using the ChipPlanner with a ProASICPLUS device no longer causes Compile to stall.

27864 - Changing the device after setting floorplanning constraints in ChipPlanner no longer causes Designer to stop functioning.

29400 - In the hierarchy display, selecting a block shows the selection of the elements of that block and the block itself. Also, assigning or locking the block shows the elements of that block as assigned, and the block itself as assigned and locked.

Layout - Axcelerator

31657 – Layout with effort level set greater then 3 may fail is region constraints contain a RAM macro. In order to run layout with a region that contains a RAM macro, start by running layout with effort less than 4, lock the RAM placement, and re-run layout with effort greater than 3. This issue has been resolved.

PinEditor

29753 - If you use the APA075-TQ144 device and package combination and use pin 30 on this package, you must modify your last_placement.gcf file before you open your design in v5.0. The R1-2003 SP3 update assigns pin 30 on this package to an invalid location and this assignment must be deleted in the last_placement.gcf for your ProASICPLUS design. Failure to do so causes Designer to display an error when you open your ADB design file. This issue has been resolved.

ACTgen

23114 - The valid width range for a standard barrel shifter is 2 to 63, and the valid width range for a shift register and a pipe-lined barrel shifter is 2 to 99. The ACTgen Macros Reference Guide has been updated with the correct information.

Import

20984 - Do not import the "lastplcmnt.gcf" file for incremental layout. Please export the GCF file and use it instead. This issue has been resolved.

29802 - Designer may exit prematurely if an empty region is specified in a GCF file contains a RAM location. This issue has been resolved.

SmartPower

30096 - Some UNIX users may see the message "Invalid imagelist handle passed to API" displayed in the console window when starting SmartPower. You can ignore this message.

PinEditor

32022/32266 - An issues with set_io constraints and promotion of high fanout nets to globals have been resolved.

Timer

29668 - A discrepancy in the slack reported inhe expanded paths and list of paths have been resolved.

29654 - An issue with adding stop points using wildcards have been resolved.

29117 - An issue with an anomalous delay reading reported when the data pin of a CM8 module is connected to the clock network has been resolved.

29114 - An issue with adding new paths to the path set to Timer has been resolved.

28309 - An issue with calculating clock skew on the Axcelerator family has been resolved.

29260 - An issue with ordering the display by slack has been resolved.

30052 - An issue with Timer requiring “calculate delays” to be selected in order to display violations has been resolved.

29630 - An issue with Timer printing text to the unix console while generating a report has been resolved.

28575 - An issue with the default register to register path through asynchronous RAM has been resolved.

28673 - An issue with Timer slack calculation has been resolved.

New Known Issues and Workarounds

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Click any of the listed issues for a description and workaround.

Libero Installation

31789 – vdconfig.exe errors when installing Libero 5.0 on Win98 or NT. 

Libraries

26434 - In ProASIC and ProASICPLUS families, FIFO Flags do not behave properly for LEVEL signal. The LEVEL signal interpretation is wrong in R1-2003. In simulation models, the value is one more than it should be. This issue was resolved in Libero/Designer v5.0.

Project Manager

30223 – Libero does not save project files during exit if ViewDraw is open. 

32132 – HDL checker displays error message if “when” is used in statement line.

32146– ModelSim does not detect changes in VHDL Code in post synthesis simulation.

WaveFormer Lite

22688 – WaveFormer Lite comes up in Evaluation Mode if there is a license issue.

Synplify

25621 – Synplify requires additional logic level for large decoder in APA designs.

20322 – Synplify Limits the maximum fanout to 10 for Axcelerator devices.  

Designer New Known Issues and Workarounds

ACTgen - ProASICPLUS

31444 – Deeply cascaded FIFOs generated in ACTgen may be generated incorrectly.

Back-Annotation - Axcelerator

32047 – The SDF back-annotated timing for the BIBUF macro does not take into account the net delay on the data to PAD path.

BSDL Generation - SX-A/SX-S

31327 – Attempting to generate a design specific BSDL file for the following device/package combinations may cause Designer to exit prematurely.

Device Package
A54SX72A 624 CCGA
A54SX72A 484 FBGA
A54SX72A 256 CQFP
RT54SX32S 256 CCLG
RT54SX32S 256 CQFP
RT54SX32S 624 CCGA
RT54SX72S 256 CQFP

ChipPlanner - ProASICPLUS

31447 – Repeated importing a GCF file which contains a region constraint creates multiple redundant regions in ChipPlanner.

30538 – Running Designer repeatedly with region constraints may cause Designer to create multiple redundant regions in ChipPlanner.

Fuse - Axcelerator

30653 – Attempting to generate a fuse file after assigning an additional VREF pin to a placed-and-routed design without re-running layout can cause Designer to exit prematurely. Run layout with incremental fixed “on” before running the “Fuse” command.

Scripting

23034 - Due to limitations in the Tcl language syntax, bracket characters “[“ and “]” commonly used in bus notation must be escaped.

Timer

29274 – Timer does not take clock exceptions into account when computing slack in the expanded path window.

29267 – Timer GUI display does not update when a script is run. Actel does not recommend running Timer scripts when the Timer GUI is active.

Layout - Axcelerator

31150 – RTAX2000S designs created by Designer 5.0 must be re-routed. Users can run layout with incremental placement set to “fix” in order to preserve the placement of the design.

Import

20984 - Do not import the "lastplcmnt.gcf" file for incremental layout. Please export the GCF file and use it instead.

Download and Install Libero IDE v5.0 SP1

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The version of software that you requested is no longer the most current version available. Please download the most recent software update.

If you need this specific version of software, please contact Actel Tech Support:
Email: soc_tech@microsemi.com
Phone: 1.800.262.1060