Libero IDE v5.0 Release Notes
Thank you for your interest in Actel's Libero Integrated Design Environment
(IDE) v5.0 . These v5.0 release notes outline new features and benefits,
new device support, known limitations, and other information about this
release.
Libero IDE v5.0
Synplicity Synplify AE 7.3
Mentor Graphics ModelSim AE 5.7b
SynaptiCad WaveFormer Lite AE 9.0u
Mentor Graphics ViewDraw AE 7.7
Designer v5.0
Actel FlashPro v3.1
Actel Explorer
Tool Profiles setup and management - New “Tool
Profiles” feature enables you to select synthesis, simulation, and
stimulus tools to be used for a project. This is for 3rd party tools where
the interface between Libero and the tool has been customized (integrated)
to ensure seamless passing of project files between the tools. A default
configuration is provided with the release. Profiles are preserved from
one Libero release to the next. Access Tool Profiles from Options > Profiles
on your main menu.
New Project Wizard - When starting a new project within
Libero, the New Project Wizard guides you in selecting all items necessary
to set up your project. This wizard will help you setup your project name,
location, family, HDL type, tools/profiles, and design files. At the end
of the wizard, a project contents summary is provided. Access your New
Project Wizard from File > New Project on your main menu.
“Find in Files” feature - This feature allows
you to search for words, files, and strings, specify types of files, and
browse for locations to be searched. Access Find in Files from Edit > Find
in Files on your main menu.
Mentor Graphics' LeonardoSpectrum Synthesis Integration - Libero
IDE supports launch and flow of data files for LeonardoSpectrum. (Check “New
Issues and Workarounds” for specific issues in this interface). LeonardoSpectrum
must be obtained directly from Mentor Graphics.
Mentor Graphics' Precision Synthesis Integration - Libero
IDE, supports launch and flow of data files for Precision. Precision must
be obtained directly from Mentor Graphics.
User defined .do file - It is now possible to select
a user defined .do file for simulation in addition to or alternatively
to the automatic .do file created by Libero. Select your choice of .do
file from the Options > Project Settings > Simulation on your main
menu.
State Display - Libero now displays the current working
state in the Process Window (e.g. Post Synthesis). Libero displays a green
checkmark when a particular process has been completed successfully.
Save-As Project - This feature allows you to save your
entire project, including all files and subdirectories, to a different
location.
Waveformer Lite input files are now based on the current project
state - Libero passw the HDL file based on the current project
state (HDL Source files for Pre-synthesis state, Designer/.vhd |.v for
Post-synthesis state, Designer/ ba.vhd|ba.v file for Post-Layout state)
to Waveformer Lite. You can also choose to pass specific HDL files for
stimulus generation by right clicking the hierarchy block, then selecting
Stimulus, then choosing the proper files to pass to WaveFormer Lite.
Default simulation resolution - Simulation resolution
is now based on device family. The faster Actel devices (Flash, SX-A, and
Axcelerator) have a default simulation resolution of 1 ps. All other families
are 1 ns. You may want to shorten the default simulation run time when
simulating faster Actel devices.
VHDL Package Files Order - VHDL coding standards allow
for file dependencies and it is sometimes necessary to establish and preserve
a specific order of the package files for simulation or synthesis. In v5.0,
you can now explicitly manage the order of your VHDL package files. When
you use Options > VHDL Package Files Organization, Libero locates all
.vhd files within the project and displays them (after they are imported
into the project as VHDL Package files). In the VHDL Package Files Organization
tool, use the Up and Down arrows to change the sequence of a highlighted
file. Alternatively, you can drag a file name up or down in the list.
Use of external HDL Text Editor within Libero - In Preferences,
you can choose to use either the built-in Libero text editor or an external
editor. Actel recommends that you only use one editor to make changes in
a given project. If a file is open in the built-in editor, Libero notifies
you if the file is modified on disk. Set up your Text Editor from File > Preferences > Text
Editor on your main menu.
Unknown Hierarchy - If Libero is unable to determine
the hierarchy of a file, Libero displays it under an “Unknown Hierarchy” tree,
not under the Design Root.
Log window automatically clears upon project closing – Upon
importing multiple designs in one Libero session, the Log Window includes
information on all designs active in the session. In the File > Preferences > Log
Window options box you may select a “Clear Log Window Automatically” option
that, when checked, enables the log window to be cleared whenever a project
is opened or closed. This option is selected by default.
Designer New Features and Enhancements
ProASIC/ProASICPLUS
Customers using ProASIC or ProASICPLUS devices should
refer to the following application note for additional information on using
Designer 5.0 with their existing designs: ProASIC
and ProASICPLUS Design-Flow Migration to Designer v5.0
MultiView Navigator - The MultiView Navigator is Actel’s
new interface for design physical design constraints and viewing. This
interface includes the ChipPlanner, PinEditor, I/O attribute editor and
Netlist Viewer. The MultiView Navigator allows for improved crossprobing
between these tools, as well as introducing new “undo/redo” and
find capabilities.
ChipPlanner - ChipPlanner is Actel’s new graphical
floorplanning tool for the ProASIC, ProASICPLUS, and
Axcelerator families.
For ProASICPLUS customers with existing constraints,
please refer to the following application note, available from http://www.actel.com:
Keeping
Existing Constraints when Using the ChipPlanner with ProASICPLUS
Reports - 20503 - “File” > “Find”,
and “File” > “Find Next” have been added to
the reports interface.
Timer - For users of the ProASIC and ProASICPLUS devices,
a new tech brief is available which
discusses using Timer with the ProASIC
and ProASICPLUS devices.
20807 – The Problem was: In ModelSim 5.5e, simulation
would not proceed if clock_stop_time= xe+00x ns. If the test
bench clock_stop_time is in expression as xe+00x ns, i.e. 2e+008ns,
the simulation cannot process more than one clock cycle.
Workaround was: Change test bench clock_stop_time to 2e8 ns or
200000000 ns.
Note: This workaround applies to clock_offset as well. To implement 200ms
clock offset, change the expression of test bench clock_offset to 2e8
ns or 200000000 ns.
This workaround is no longer needed; the problem is resolved
in ModelSim 5.7b
23663 – The Problem Was: Comment Out and Uncomment Out
option in Text Editor should not work on non-source code file text. Currently
Libero's Text Editor allows you to Comment Out or Uncomment Out files
other than source code files (such as .edn, .sdf, bitstream, and .afm
files). Doing so may modify these files.
Workaround: Do not Comment Out or Uncomment Out non-text files
(.edn, .sdf., bitstream, .afm, or other source code files in the Text
Editor).
This workaround is no longer needed.
26333 – The Problem Was: Error in source code causes Waveformer
Lite to close. After opening a project, setting a root, and
attempting to create a stimulus with WFL, WFL may immediately close
if there is an error in the source code.
Workaround: Use Check HDL or another compiler to ensure syntax
is correct prior to invoking Waveformer Lite to create a testbench. For
schematic designs, use Save+Check to ensure the schematic drawings are
correct.
This workaround is no longer needed.
25284 – The Problem was: Implementing an IB33U Macro will
replicate itself, then create an improper netlist and fail compile.If
you instantiate a IB33U macro as follows:
IB33U R1 // instantiated macro name = IB33U, instance name = R1
//Input Port
(.PAD(J5_spi_en),
//Output Port
.Y(spi_en_pu));
Then when you run synthesis in Synplicity 7.2 and compile in Designer
you
get the following error:
PROBLEM [port_connected_twice]:
The external port "J5_spi_en" is connected to at least 2 instances:
" R1_0" and "R1".
Synplicity is instantiating two IB33U for same signal J5_spi_en.
R1_0 : IB33U
port map(PAD => J5_spi_en, Y => spi_en_pu_0);
R1 : IB33U
port map(PAD => J5_spi_en, Y => spi_en_pu);
Workaround: Use syn_keep attribute in synplicity for "spi_en_pu",
which is output of IB33U.
//***************** pull_up.v ********************/
wire spi_en_pu /* synthesis syn_keep=1 */;
This workaround works for Verilog and for VHDL, however it does not
work for ViewDraw. Please contact the Actel Hotline for more information.
Workaround: Use syn_keep attribute in synplicity for "spi_en_pu",
which is output of IB33U.
//***************** pull_up.v ********************/
wire spi_en_pu /* synthesis syn_keep=1 */;
This workaround is no longer needed.
Designer Resolved Issues
ACTgen
22774 - When generating a PLL for ProASICPLUS in ACTgen,
a secondary frequency was displayed when defaults are chosen even though
there is no real secondary frequency. This issue has been resolved.
26110 – ACTgen now accepts spaces in the project name and project
path.
Libraries
23906 - Vital libraries no longer require that the entity be compiled
before the architecture.
Import
24264 - If a file is referenced for import in the GCF using a “/” character,
compile now recognizes the “/” character and can read the
file.
Device Selection Wizard
26972 - Changing the default I/O standard in an existing SX-A design
will no longer invalidate layout.
PinEdit
27399 - PinEdit now shows the I/O tile coordinates for ProASICPLUS devices.
Click any of the listed issues for a description and workaround.
Project Manager
Interface to LeonardoSpectrum: Opening a project: Blank Project
Files (Input) screen. When LeonardoSpectrum is launched from
within Libero the LeonardoSpectrum “Input window” may be
blank and may display the incorrect Actel family. In the “Information” window,
you will see a message that states “Message from Libero: Please
Press Enter”.
Workaround: Put the cursor in the information screen press the
enter key to refresh the screen and display the correct input project
files and family
26214 – Interface to LeonardoSpectrum: Finding the synthesized
netlist from LeonardoSpectrum. When launching and using LeonardoSpectrum
from within Libero, Designer may not find the synthesized netlist and
Libero will not allow you to “Run Designer”. This is because
LeonardoSpectrum may have saved the log file in the directory of a
previous project.
Workaround: In the LeonardoSpectrum Tools > Options dialog
box, uncheck the “Automatically Save and Restore Current Work Directory” check
box.
29888 – Libero stops when you close Print Preview with
X. If you close the Print Preview window in Libero with the “X” in
the top left window corner, Libero crashes.
Workaround: Do not use the “X” close window button
to close the window. Use the “Close” button on the Print
Preview window.
30223 - Libero does not save the project files during exit if
ViewDraw is open. If you close Libero with the “X” close
window button, Libero may not save the project files. The also occurs
if you user File > Exit or Alt+ F4. ViewDraw prevents Libero from
writing to the project file.
Workaround A: Close ViewDraw before closing Libero -or-
Workaround B: Save Project inside Libero before you close it with
the X button.
WaveFormer Lite
25903 – Waveformer Lite v9.0: Simulation fails with the
Waveformer Lite testbench due to (any family) Use clause. The
(family) library is not being defined as a library before it gets used
in “use family.components.all” inside the testbench file.
This only happens in designs that use the components package in the
VITAL library because you do not want to pre-declare the components
before they are instantiated.
Workaround: if you do NOT want to declare component declarations
in the source code before instantiating, add this in the source code:
library < family> ;
use .components.all
Add the above in the source code in lieu of specific component declarations.
Manually add in the library statement: library <fam> in the WaveFormer
Lite-generated testbench because WaveFormer Lite only copies the use <family>.components.all
from the source VHDL but not the library <family> statement that
needs to be added to be sure ModelSim works correctly.
Note: This affects all families. A user who declares all his components
before instantiation should not see this problem, because the VHDL source
code does not need the “use<family>.components.all” statement.
29207 – WaveFormer Lite 9.0d opens default_.btm regardless
of what .btm file you select. When you double-click a *.btm
file in the file manager, WFL always opens up the default _tbench.btim
file, even if you have saved several *btim files and named them successfully
(such as x.btim, y.btim, z.btim, etc.).
Workaround: When you attempt to open your *btim files, a pop-up
window appears and asks “default_tbench.btim has changed. Do you
want to save the changes”? Click No. The *btim file you selected
will then open correctly.
28399 – Cannot create a btim file that is created in a
different state. If you have an unsigned port in your RTL
code, Synplify changes it to std_logic. For example:
RTL: A: in unsigned (7 down to 0)
Post_Layout: A: in std_logic_vector (7 down to 0)
If you create your testbench in Pre-Synthesis, this results in a stimulus
with unsigned elements, which is acceptable, but if you open the btim
file in the Post-Layout state to modify the waveforms, WaveFormer Lite
still generates a stimulus with unsigned elements. This is not acceptable
to ModelSim and ModelSim will note a mismatch.
Workaround: Click the signal inside the WaveFormer Lite window.
Open the Edit Signal Properties dialog box and change the data type from
unsigned to std_logic_vector. The testbench now has the desired data
type.
29143 – WaveFormer Lite testbench gives bit & bit
vector errors in ModelSim. WaveFormer Lite 9.0 uses testbench
type std_logic for clock signals. Only non clock signals can be changed
to bit or bit_vector data types.
Workaround: All clock signals must use the “std_logic” data
type. Do not use “bit” data type for clock signals. For non
clock input signals, from the WFL waveform GUI, right-click the signal
and select the Edit Selected Signals and change the VHDL (through the
pull down menu) from “bit” to “std_logic” data
type. This pull-down menu does not work for clock signals, as they are
greyed out. You must use std_logic as the data type for all clock signals.
29474 – Too many “else if” statements causes
parser stack overflow in WaveFormer Lite. A design that contains
too many “else if” statements following an “if” causes
a stack overflow in WaveFormer Lite, and a testbench will not be created.
Example: “if…else if, else if, else if”.
Workaround: Synthesize the design, then use the structural netlist
to generate a waveform. The structural netlist does not contain if/elseif
statements. WaveFormer Lite can create a testbench from the structural
netlist.
29761 – WaveFormer Lite 9.0 opens existing top_.btm when
creating new stimulus. With WaveFormer Lite 9.0, if you try
to create a new stimulus on an existing top level, WaveFormer Lite
opens the last/existing <default_top>_tbench.btm file, instead
of starting from scratch as you would expect.
Workaround:
(1) Exit the existing .btim file (do not close WaveFormer Lite)
(2) Answer Yes when the pop up window asks "Do you want to save
the file"
(3) Click File > New Timing Diagram
(4) Click the “Extract the MUT ports into Diagram icon” (located
on the far right in the WFL toolbar)
(5) The I/O ports will be loaded into the Waveform Window.
(6) Draw and save the waveforms, then export testbenches.
ViewDraw
28159 – ViewDraw vs. VHDL Naming issue: When using a mixed
VHDL and Schematic design, you must currently limit your names to those
legal in both VHDL and schematic. A top level schematic called
temp-F that is acceptable in the ViewDraw environment is illegal syntax
in VHDL. VHDL requires backslashes before and after the names (i.e.
\temp-F\ as the entity name instead of the original name temp-F).
Workaround: In mixed VHDL (and Verilog) designs with schematic,
make sure you use syntax common to both.
Designer Software New Known Issues and Workarounds
ChipPlanner
27864 - Changing the target device after using the ChipPlanner with
a ProASICPLUS device may cause Compile to stall.
27864 - Changing the device after setting floorplanning constraints
in ChipPlanner may cause Designer to stop functioning. To change devices,
re-import the netlist into a new design.
28117
- Changing the name of a region does not take affect until after you
click the “OK” button.
27347
- The ChipPlanner does not warn you if the same macro is assigned to
two separate regions. However, layout detects this error and fails.
29980 - ChipPlanner may show the status of some routed nets as unrouted
in the Axcelerator device even after layout has succeeded. The nets are
routed and the status message is in error. If layout succeeds, the device
has been routed.
29548 - When viewing fan-in nets leading to RAM elements in the ChipPlanner,
some nets may not be drawn all the way to the memory and seem to terminate
before touching the RAM. This is a display issue and the nets are actually
connected to the memory block.
29400 - In the hierarchy display, selecting a block shows the selection
of the elements of that block but not the block itself. Also, assigning
or locking the block shows the elements of that block as assigned, but
the block itself does not show as assigned or locked even though the
block and its contents are assigned.
PinEditor
29753 - If you use the APA075-TQ144 device and package combination and
use pin 30 on this package, you must modify your last_placement.gcf file
before you open your design under v5.0. The R1-2003 SP3 update assigns
pin 30 on this package to an invalid location and this assignment must
be deleted in the last_placement.gcf for your ProASICPLUS design.
Failure to do so causes Designer to display an error when you open your
ADB design file.
ACTgen
23114 - The valid width range for a standard barrel shifter is 2 to
63, and the valid width range for a shift register and a pipe-lined barrel
shifter is 2 to 99.
Scripting
23034
- Due to limitations in the Tcl language syntax, bracket characters
“[“ and “]” commonly used in bus notation must
be escaped.
24270
– The Tcl processor does not create a new line for any “put”
command with an empty string.
Import
20984 - Do not import the "lastplcmnt.gcf" file for incremental
layout. Please export the GCF file and use it instead.
29802
- Designer may exit prematurely if an empty region is specified in
a GCF file contains a RAM location.
I/O Attribute Editor
29876 - The Edit > Copy option from the tools menu will not allow
users to copy and paste data from the I/O Attribute Editor.
SmartPower
28172
- The clock frequency must be set before the data toggle rate. Failure
to do so causes SmartPower to dispay the incorrect data toggle rate.
30096
- Some UNIX users may see the message "Invalid imagelist handle
passed to API" displayed in the console window when starting SmartPower.
You can ignore this message.
Layout
29807 - Do not use the memory.gcf file generated by ACTgen. This file
is now obsolete and importing this file causes layout to fail.
BSDL
27234
- Attempting to export a BSDL file may cause Designer to display an
error
