Designer v8.3 Release Notes
(Mar 31, 2008)
Thank you for your interest in Actel's Designer v8.3 FPGA Physical Implementation Software.
All Fusion, IGLOO, IGLOOe, ProASIC3L, ProASIC3, and ProASIC3E users are required to upgrade your existing designs to Libero IDE/Designer version 8.3. Important place-and-route software changes have been made that must be factored into your design to ensure proper handling of all conditions.
In March 2008, it was discovered that a potential advanced optimization could cause a logic gating of a global signal. This optimization is part of a set of other routing optimizations that could be invoked if a user sets the Routing High Effort Mode in the Advanced Option of the Layout. This is limited to Fusion, IGLOO, IGLOOe, ProASIC3L, ProASIC3, and ProASIC3E designs.
When opening an existing Fusion, IGLOO, IGLOOe, ProASIC3L, ProASIC3, or ProASIC3E ADB file with release v8.3, a message may instruct you to re-route your design by checking the "Route incrementally" checkbox in the Layout dialog box. The impact on performance due to any incremental routing update is expected to be minimal.
IGLOO PLUS
Libero IDE v8.3 introduces support for Actel's new IGLOO PLUS low-power high I/O count family. This new 5 microwatt (5 µW) I/O-optimized family offers up to 64 percent more I/Os than the award-winning IGLOO family supporting independent Schmitt trigger inputs, hot swapping, and Flash*Freeze bus hold. The low-power consumption and I/O optimization of the IGLOO PLUS family makes it an ideal solution for portable electronics in consumer, industrial, communications, medical, and test applications, particularly those employing I/O-intensive memory bus manipulation, general-purpose I/O expansion, sequencing, interface translation, storage and human interface touch screen and key pad technology.
The following devices and packages are supported in this release:
| Device |
Package |
Speed Grade |
Temperature Range |
| AGLP030V2 |
CS201 |
STD |
COM, IND |
| AGLP030V5 |
CS201 |
STD |
COM, IND |
| AGLP060V2 |
CS201 |
STD |
COM, IND |
| AGLP060V5 |
CS201 |
STD |
COM, IND |
| AGLP125V2 |
CS281 |
STD |
COM, IND |
| AGLP125V5 |
CS281 |
STD |
COM, IND |
RTAX-S Performance Improvement
Extensive radiation total dose testing on RTAX-S material produced over several years has revealed that the radiation propagation delay derating of 10% at 100 Krads, 20% at 200 Krads and 30% at 300 Krads were conservative. These deratings have been reduced to 3% at 100 Krads, 4.5% at 200 Krads, and 6% at 300Krads. As a result, RTAX-S users can expect a performance increase up to 7% at 100Krads, 15% at 200 Krads, and 23% at 300Krad.
IGLOO New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| M1AGL250V2 |
VQ100, FG144 |
STD |
COM, IND |
| M1AGL250V5 |
VQ100, FG144 |
STD |
COM, IND |
ProASIC3L New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| M1A3P600L |
PQ208, FG144, FG256, FG484 |
STD, -1 |
COM, IND |
ProASIC3 New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| A3P015 |
QN68 |
STD, -1, -F |
COM, IND |
| A3P015 |
QN68 |
-F |
COM |
Fusion New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| M1AFS250 |
QN180, PQ208, FG256 |
STD, -1, -2 |
COM, IND |
| U1AFS250* |
FG256 |
STD |
COM, IND |
| U1AFS600* |
FG256 |
STD |
COM, IND |
| P1AFS600** |
FG256, FG484 |
-1 |
COM, IND |
| P1AFS1500** |
FG256, FG484 |
-1 |
COM, IND |
* The U1AFS devices support the Advanced Mezzanine Card (AMC) reference design starter kit, developed in partnership with MicroBlade, Inc. For more information regarding the AMC reference design or the U1AFS devices, please contact Mike Brogley (mike.brogley@actel.com, 650.318.4982).
** This release also adds support for P1AFS600 and P1AFS1500 devices. The P1AFS devices support reference designs and development kits developed in partnership with Pigeon Point Systems. For more information regarding these kits or the P1AFS devices, please contact Mike Brogley (mike.brogley@actel.com, 650.318.4982).
Improved Flash*Freeze Flow for IGLOO, IGLOO PLUS, and ProASIC3L
One of the key benefits of Actel's Flash*Freeze mode is the ability to preserve the state of all internal registers, SRAM content, and I/Os (IGLOO PLUS only). This feature enables seamless continuation of data processing before and after Flash*Freeze, without the need to reload or reinitialize the FPGA system. A new Flash*Freeze management IP offers a robust RTL block that ensures clean clock gating of all system clocks before entering and upon exiting Flash*Freeze mode. This IP also provides the option to perform housekeeping prior to entering Flash*Freeze mode.
Libero IDE v8.3 includes a new, convenient, and intuitive design flow for configuring and integrating Flash*Freeze into an FPGA design. Flash*Freeze type selection and management IP can be generated by the Libero IDE core generator and instantiated as a single block in the your design. This block will include an INBUF_FF macro and the optional Flash*Freeze management IP, which includes the ULSICC macro. The INBUF_FF macro is driven by the design Flash*Freeze port in both type 1 and 2. The ULSICC macro is used in type 2 to control the entry into Flash*Freeze mode.
Existing designs (ADB) utilizing Flash*Freeze will be converted automatically when opened with v8.3. When converting a design, the status report is no longer available from the menu. You must recompile the design to have the status report available. For designs using Flash*Freeze Type1, users must regenerate the programming file using v8.3.
Note: Using v8.3, you can instantiate only one Designer Block in the design. When using a Designer Block in a Flash*Freeze design, the Flash*Freeze macro, either Type 1 or Type 2, must be inside of the Designer Block. Refer to Known Issue number 75337.
New netlists must have the INBUF_FF macro instantiated in the design such that the Flash*Freeze port drives the macro. You can generate and instantiate the Flash*Freeze management IP from the Libero IDE Catalog, or, manually instantiate the INBUF_FF macro. Actel recommends that you manually instantiate the INBUF_FF macro when using Flash*Freeze type 1. If you are using Flash*Freeze Management IP for the Flash*Freeze type 1, please read Known Issue number 75290.
For more information please see the Libero online help and the Flash*Freeze and Low-Power Modes Technology in IGLOO and ProASIC3L Devices section of the handbook.
IGLOO, IGLOO PLUS, and ProASIC3L LVCMOS 1.2 v I/Os
1.2 volt LVCMOS I/O technology is the lowest VCCI standard available and is now available for ProASIC3L, 1.2 volt IGLOO, and 1.2 volt IGLOO PLUS devices. LVCMOS 1.2 is the default I/O selection for these devices. To further ensure low-power operation, the drive strength is set at 2 mA for all devices with the exception of the IGLOO AGL030V2 and AGL015V2 where the drive strength is set to 1 mA.
Use of 1.2 volt I/O allows operation of IGLOO, IGLOO PLUS, and ProASIC3L devices, both Core and I/Os, from a single 1.2 volt power supply. 1.5 volts is still required for programming.
IGLOO and ProASIC3L PLL/CCC Update
Existing IGLOO, IGLOOe, and ProASIC3L designs that have a PLL/CCC core may have an invalid configuration. When you open your design with v8.3, a check will be run and a message will instruct you to regenerate the programming file if necessary.
SmartPower New Features
You can now enter your own temperature and voltage values to device modes, such as Active, Standby, Flash*Freeze. This allows you to create additional "what-if" scenarios or profiles to test your design under various operating conditions. This feature is available for IGLOO, IGLOO PLUS, ProASIC3L, ProASIC3, and Axcelerator.
Automatic glitch filtering during the VCD read process removes spurious transitions based on the minimum pulse width for the target device, providing a more accurate analysis of power.
You can now extract "Probabilities" from VCD files. In addition to extracting the average frequency of pins from a VCD file, SmartPower will now automatically compute the "probabilities" (or likelihood) of enable signals being active. The probabilities, expressed in percent, are used with the enable rates feature to provide greater accuracy for RAM/FIFOs and tri-stated IOs.
Repair of Minimum Delay Violations
The Advanced Layout Option to repair minimum delay violations for Fusion, ProASIC3E, and IGLOOe devices has been enhanced to take advantage of programmable delays on I/O Input buffers. The feature inserts delay in paths where the minimum delay in not being met, while simultaneously checking maximum delays to ensure no violations are being introduced.
Note: Do not use Min Delay Repair for AFS600 and AFS1500. Refer to Known Issue number 75276.
Designer v8.3 is supported on Windows XP Pro, Windows Vista Business, Unix Solaris, and Red Hat Linux.
Note: Designer v8.3 is the last version supported on Unix Solaris.
For more information, view the complete System Requirements.
Designer v8.3 requires a current Designer v8.0 license. Register for a free Designer Evaluation or Gold license, or contact your local Actel Sales office to purchase a Designer Platinum license.
Unless otherwise noted, these issues apply to all devices.
Block Flow/Flash*Freeze
75337 – Using v8.3, you can not instantiate more than one Designer Block in the design. (IGLOO/e, IGLOO PLUS and ProASIC3L)
When using a Designer Block in a Flash*Freeze design, the Flash*Freeze macro, either Type 1 or Type 2, must be inside of the Designer Block.
Synplify/Synplify Pro
75290 – For Flash*Freeze type 1 design, "syn_noprune" needs to be manually added in the RTL. (IGLOO/e, IGLOO PLUS, ProASIC3L)
If you use the Flash*Freeze management IP for Type 1, Synplify will remove the INBUF_FF macro during synthesis.
Workaround: Apply the "syn_noprune" attribute to the instance containing the INBUF_FF macro. In the example below, myFF is the Flash*Freeze core name that is used to generate the core from Libero or SmartGen, and myFF_0 is the instance name of this core in the next level of hierarchy.
Example in VHDL:
architecture DEF_ARCH of Top is
attribute syn_noprune : boolean;
attribute syn_noprune of myFF_0: label is true;
begin
myFF_0 : entity work.myFF
port map(Flash_Freeze_N => Flash_Freeze_N);
end DEF_ARCH;
Example in Verilog:
module Top(
Flash_Freeze_N,
);
input Flash_Freeze_N;
myFF myFF_0 (.Flash_Freeze_N(Flash_Freeze_N)) /* synthesis
syn_noprune=1 */;
endmodule
SmartGen Core Configuration
74197 – Multiplier error when turning on the compile resource with a 24x9 configuration (ProASIC3/e)
63342 – SmartGen's interpretation of .hex file is incorrect
62366 – When selecting an EDAC RAM, the selected die may not be the same as the currently selected device (AX)
74505 - Memory content is not flushed out between different Init Clients
Prototype Flow
74499 - "Generate Prototype" flow is not supported when Designer Blocks are implemented in the design. (AX, RTAX-S)
This flow is not currently supported.
Designer
75316 - Layout error will occur if the Flash*Freeze pin is set to RESERVED or VREF (ProASIC3L, IGLOO, ProASIC3E)
Currently the user is not prevented from setting the Flash*Freeze pin to RESERVED or VREF using I/O Attribute Editor in MVN or though PDC. This restriction will be implemented in a future release.
Workaround: If you have a Flash*Freeze port in your design, make sure you do not block the Flash*Freeze pin by setting it to RESERVED or VREF.
75276 - Designer freezes when using Min Delay Repair for AFS600 and AFS1500 devices with external hold violations.
There is no problem in designs with minimum register to register violations. Do not use Min Delay Repair for AFS600, AFS1500.
SmartTime
72944 - The I/O timing numbers reported in SmartTime does not always follow the trend
Programming File Generation
72106 – M1AFS600 requires STAPL generated from Designer v8.1 or higher
75493 - Fusion analog designs generated on Linux have invalid programming/STAPL files
Workaround: Use Windows XP/Vista to generate programming/STAPL files for Fusion analog designs
