Designer v8.2 SP1 Release Notes
(Feb 19, 2008)
Thank you for your interest in Actel's Designer v8.2 Service Pack 1 FPGA Physical Implementation Software.
IGLOO
This release introduces support for the following new devices:
| Device |
Package |
Speed Grade |
Temperature Range |
| AGL015V2 |
QN68 |
STD |
COM, IND |
| AGL015V5 |
| AGL1000V2 |
FG144, FG256, FG484 |
STD |
COM, IND |
| AGL1000V5 |
Fusion Calibration
You can now achieve more precise voltage measurements with Fusion by using a new Calibration IP feature within the SmartGen Analog System Builder core and factory programmed calibration coefficients. Calibration coefficients for each Fusion device are created by Actel and stored in the Fusion Flash Memory Block Nonvolatile Memory (NVM) prior to shipment. This new Calibration feature uses these coefficients to apply corrections to the Fusion measurements for the final system implementation. Better than 1% accuracy may be achieved when using the ADC and pre-scalers available in the Fusion device. Use of other Fusion features, such as embedded flash and SRAM blocks, analog functions, the FPGA fabric, and an optional soft processor core allow for a highly integrated and seamless calibration solution. Flashpro v6.2 Service Pack 1 (SP1) must be used for the calibration operation.
More information is available in the Temperature, Voltage, and Current Calibration in Fusion FPGAs Application Note and the ASB Advanced Option > Calibration section in the Online Help.
Flashpro v6.2 SP1
FlashPro v6.2 SP1 must be used with Libero IDE v8.2 SP1 for the Fusion calibration feature noted above. The Scan Chain operation in the FlashPro software will enable the programming mode for each Fusion device in the chain. This may interrupt any NVM user access that may already be in progress.
Notes:
- The Programming operation will be canceled, if the selected Fusion device is already calibrated and the programming file overlaps the calibration data. In this case, you must regenerate the Analog System Builder core with the Calibration feature enabled and regenerate the flash memory using the Libero IDE v8.2 SP1 release or newer.
- Users who want to use the Calibration IP feature but do not have Fusion devices with pre-programmed coefficients must use a factory-generated POPULATION.stp STAPL file.
See the Temperature, Voltage, and Current Calibration in Fusion FPGAs Application Note for more details.
Designer v8.2 SP1 requires a current Designer v8.0 license.
Register for a free Designer Evaluation or Gold license, or contact your local Actel Sales office to purchase a Designer Platinum license.
Unless otherwise noted, these issues apply to all devices.
IBIS Files for IGLOO AGL015
74189 - IBIS models for the AGL015 are not yet available. An error will be shown, if you attempt to get IBIS models from this release.
SmartTime
74057 – SmartTime automatically annotates Minimum Pulse Width on ACMCLK to 10 MHz. In Fusion designs, the recommended clocking scheme is to use the NGMUX to choose between a slow initialization clock, which is limited by the ACMCLK that has a maximum output of 10 MHz, and a Fast System Clock, which can be 40 or 80 MHz. Both clocks come from the PLL and the INIT_DONE signal is used as the Mux control.
Due to the Minimum Pulse Width annotation by SmartTime, SmartTime shows 10 MHz for both fast and slow clock domains, and this prevents the actual timing from being displayed.
Workaround: Put a False Path on the ACMCLK pin.
