Introducing Cortex-M1 Support
This release introduces Cortex-M1 software support for Actel FPGAs. The Fusion M1AFS600 and ProASIC3 M1A3P1000 are the first of many devices. Program File (PDB/STAPL) generation is also enabled for these devices.
| Device |
Packages Available |
| M1AFS600 |
208 PQFP, 256/484 FBGA |
| M1A3P1000 |
208 PQFP, 144/256/484 FBGA |
10% average performance gains for Fusion, IGLOO, and ProASIC3 devices can be obtained through new techniques in Layout physical optimizations. When starting layout in Designer, select Advance Layout Options and High-effort Layout. In the standard flow, the compile step in Designer modifies the netlist to make use of any efficient resources on the device, such as global networks and special macros. When the High Effort Layout is selected, the placer further changes the mapping of the logic components, while preserving the functionality of the design. The changed netlist is then used in all post-layout tools including back-annotation.
SmartPower now accounts for I/O banks static power for AX and RTAX-S devices.
Program file generation is enabled for these devices:
- Fusion M1AFS600
- ProASIC3 M1A3P1000
- IGLOO AGL600
- Fusion AFS250
The FG256 package for the AFS090 device has been re-introduced. The AFS090 in the FG256 package is now pin compatible with the AFS250 in the same package. All 5 (previously 4 of 5) of the analog quads are on the same pads as the AFS250. The layout for existing AFS090 designs will be invalidated and the design put back to the pre-compile state.
SP1 support for ARM7 M7 devices limited to M7A3P1000 and M7AFS600.
Due to the great value the Cortex-M1 32-bit soft processor core offers, Actel is now focusing development efforts on M1 devices to make them available as soon as possible. To be able to do this we are limiting our development of M7 devices that support the CoreMP7 soft processor. While we will continue to make the M7AFS600 and M7A3P1000 devices available we will not develop any other M7 devices at this time. As of this SP1, the M7 devices below are no longer supported. There are no equivalent size Cortex-M1 devices available in the software at this time. When opening an existing project for the discontinued devices below, Libero will notify you the device is discontinued. You can continue the M7 design using Libero v8.0 without the SP1, or, you can continue to use it by opening the existing adb using Designer stand-alone. Actel recommends that you switch to the recommended Cortex-M1 devices below when available. Contact your local sales office for additional information on Cortex-M1 devices.
| Discontinued |
Actel Recommendations |
| M7A3P250 |
M1A3P250 (Q4 2007) |
| M7A3P400 |
M1A3P600 (Q4 2007) |
| M7A3PE600 |
| M7AFS1500 |
M1AFS1500 (2008) |
Unless otherwise noted, these issues apply to all devices.
Synplify/Synplify Pro AE Support for Cortex-M1 Devices
The current version of Synplify/Synplify Pro AE (8.8A1) does not provide support for Cortex-M1 supported devices.
When Synplify/Synplify Pro AE is launched from the project, a message is displayed that the device is not recognized. Synplify/Synplify Pro AE will open using the same family (e.g. ProASIC3) and the smallest device within that family. You should open the Implementation Options dialog box and select the device of the same size (e.g. A3P1000 for M1A3P1000).
SmartGen
67983 – The maximum analog voltage settings for AV/AC, and AT pads on Fusion AFS devices has been finalized.
The maximum voltage allowed on an AV/AC pad is -10.5 to + 12.0 V, and 0 to +16.0 V on an AT pad. The Analog System Builder in SmartGen allows you to input up to 16.0 in the input voltage window, but if you try to assign greater than +12 V to an AV/AC pad you will get a tooltip error icon in the Analog System Builder main dialog.
67880 – Launching Analog System Builder shows "Error while executing TCL script" message. (Fusion)
In this release, the 256 FBGA package for the AFS090 was updated. Due to this update, some package pins that were previously assigned in the Analog System Builder might no longer be valid. When trying to open the Analog System Builder in v8.0 SP1, you might encounter the following error:
Error while executing TCL script: Error in command
adc_set_voltage_channel: Parameter -package_pin has illegal value at line
Workaround: To resolve this issue, you can remove the package pin assignment at the indicated line in the error message. To do so, follow the following steps:
- Go to the SmartGen directory
- Go to the Analog System design directory
- Open the *.cfg file using any text editor
- Find the line number at which the error is indicated
- Remove the package pin assignment that is indicated by:
-package_pin
- Save
- Re-open the Analog System builder.
64911 - EDAC macro will have new top level name.
If you regenerate the EDAC in Libero v8.0 or newer version, the top
level HDL wrapper will change from <corename>_top to <corename>.
In earlier releases, generating an EDAC core <my_edac> with a core name produced three files:
my_edac_top.vhd: EDAC wrapper
my_edac.vhd: RAM block
edac_#.vhd: EDAC core. Example: edac_18.vhd
In Libero 8.0, the three files will be:
my_edac.vhd: EDAC wrapper
my_edac_RAM.vhd: RAM Block
edac_#.vhd: EDAC core. Example: edac_18.vhd
Libero v8.0 or newer versions will indicate this change to the user by
giving error message:
"Error: Cannot find module <name> _top."
And/or showing a "?" in the hierarchy next to the EDAC wrapper.
If you have instantiated the EDAC top level wrapper in your design, you
need to change the name in your RTL or Schematic after you regenerated
the EDAC core.
Designer
67821 – Changes to the analog I/O pin assignments are not correctly shown in Designer. (Fusion)
The analog I/O pin assignments change when you change the package or die, or when you manually change the assignments in the Analog System Builder.Those changes are not correctly passed to Designer if the "Merge PDC file with existing physical constraints" import option is checked.
Workaround: This issue is fixed in this service pack. If you are working with a pre v8.0 SP1 project, when re-importing the netlist into Designer, uncheck the "Merge PDC file with existing physical constraints" option.
67632 - Advanced Layout "High Effort" mode is not supported for NGMUX designs. (Fusion)
When you check the "High Effort Layout" option in the "Advanced Layout" dialog, layout will use the standard flow if the design contains an NGMUX. Layout will revert back to the regular Layout flow.
The High Effort mode is also not supported for M7 or M1 devices.
SmartTime
67337 – The Min Delay data in the analysis bottleneck report is incorrect and entitled as Max Delay
67816 – Previous constraints do not appear when re-opening SmartTime.
For a design with auto-generated clocks, some constraints may not be visible after reopening the tool if you previously closed SmartTime prior to clicking the "Commit" button. Although the constraints are not visible, they are correctly taken into account in the analysis. To have access to all the constraints again, please reload your adb.
68339 - Adding false path or multicycle constraints on multiple paths in the Analysis View causes Designer to crash
When selecting multiple paths in the analysis to set a constraint on, the selector for -through is not available, and clicking on the "..." causes Designer to quit. It is still possible however to enter pin/net/instance names in the edit field. Note also that this is only a problem when more than 1 path is selected.
SmartPower
68425 - Static power contribution for Vcci for RTAX-S IO banks is excessive (RTAX-S)
Static power contribution per IO bank on Vcci is too pessimistic in SmartPower. This contribution is one order of magnitude higher than actually measured on silicon.
This will be fixed in 8.0 SP2.
67727 – Static power contribution for Vccda for IOs with Vref is missing (AX)
Static power contribution for Vccda based on Iccdiffa per IO using Vref is not currently available in SmartPower. Specific I/O technologies are: GTL+ 2.5 V, GTL+ 3.3 V, HSTL CLASS I, LVDS, LVPECL, SSTL2 CLASS I, SSTL2 CLASS II, SSTL3 CLASS I, and SSTL3 CLASS II.
