SmartTime
- Minimum Delay Constraint: A (set_min_delay) dialog is added to allow you to relax or tighten min delay constraints on specific clocks or paths. Similar to the already existing "Maximum Delay Constraint" dialog, you specify the delay for -From and -To pins, using a browse function that presents all available pins. Set_Min_Delay constraint is available for APA, A3P, AGL, AFS, AX, and RTAX-S devices.
- Bottleneck Analysis View: Complementary to the Bottleneck Analysis Report that was introduced in Libero IDE/Designer v7.3, SmartTime now includes a Bottleneck Analysis View. A bottleneck is a point in the design that contributes to multiple timing violations. In a prioritized manner, the Bottleneck Analysis view shows the specific instances that are causing the delay in terms of number of paths that are affected as well as the total delay for each instance. The bottleneck analysis view can also take you directly to the MultiView Navigator to see the location of the specific instance that is causing the delay. You can analyze the entire design, clock domains, or from — to paths.
- New Constraint Objects: SmartTime now supports "nets" and "instance" objects when setting constraints, with built-in priority management.
- Case Sensitive Constraint Names: To be consistent with available RTL coding, SmartTime constraint names are now case-sensitive.
- SDC Import/Export Options: A new dialog is provided where you can choose on SDC import to select either the user netlist (default) or an optimized netlist. In either import or export, you can choose to use either slash (/) or colon (:) separators. Colon separation is default.
- New SmartTime Report Feature: The SmartTime report now includes "Data Source". The Data Source can be either "Advanced", meaning pre-silicon estimates, or "Silicon Verified", where the data comes from actual silicon characterization.
Designer Auto-Repair of Minimum Delay Violations. A new feature in the Advanced Layout Options dialog for Fusion, A3P, IGLOO, AX, and RTAX-S devices helps to repair minimum delay violations of up to 3 ns during routing. The feature inserts delay in paths where the minimum delay is not being met, while simultaneously checking maximum delays to ensure none are being introduced.
SmartPower VCD Reader
- Glitch Filtering: This feature implements a very simple glitch filtering scheme. If the value of a signal changes twice within a user-specified glitch window limit, SmartPower ignores both transitions.
- XZ State Support: This feature enhances the VCD reader to account for 1X0 transitions (resp. 1Z0 transitions)
- New SmartPower Report Feature: The SmartPower report now includes "Data Source". The Data Source can be either "Advanced", meaning pre-silicon estimates, or "Silicon Verified", where the data comes from actual silicon characterization.
FlashPro/FlashPoint Integration. FlashPoint, historically part of the Designer tool suite, provides the interface to generate programming files for IGLOO, ProASIC3 and Fusion devices. The FlashROM, Fusion embedded flash memory, and security settings can be reset and reprogrammed using the FlashPro software.
The FlashPoint function is now integrated into the FlashPro software. By having this feature in FlashPro, you can modify the contents of the embedded flash memory or change the serialization sequence of the FlashROM contents without using Designer. Designer's program file generation from FlashPoint now by default generates a programming database file (PDB) file instead of a STAPL (STA) file. A PDB file is required to enable you to make modifications using FlashPro. When you want to change your programming settings in FlashPro simply click the "Configure PDB" button. All modifications are stored in the PDB file and FlashPro uses the information to program the device with the appropriate settings. Libero IDE/Designer does not have to be open to make these modifications in FlashPro.
Silicon Support
- IGLOO
- Libero IDE v8.0
- Introduces support for the low power IGLOO 1.2 volt core devices. Part number example: AGL030V2. See chart below for devices supported in this release.
- Renames previous 1.5 volt core devices. Part number example: AGL030V5. See chart below for devices supported in this release. Existing 1.5 volt core device designs must be re-run through route.
- IBIS Model Support: Pre-silicon IBIS models are available
Devices and Packages
| Family |
New Devices |
Packages |
Existing Device |
New Packages |
Package Updates |
| ProASIC3 |
|
|
A3P600* |
FG144
FG484 |
PQ208
FG256 |
IGLOO
1.2 V Core |
AGL030V2 |
VQ100
QN132 |
|
|
|
| AGL125V2 |
VQ100
QN132
FG144 |
| AGL600V2 |
FG144
FG256
FG484 |
| AGLE600V2 |
FG256
FG484 |
IGLOO
1.5 V Core |
AGL030V5**
(replaces AGL030) |
VQ100
QN132 |
|
|
|
AGL125V5**
(replaces AGL125) |
VQ100
QN132
FG144 |
AGL600V5*
(replaces AGL600) |
FG144
FG256
FG484 |
|
|
FG256
FG484 |
AGLE600V5**
(replaces AGLE600) |
FG256
FG484 |
|
|
|
| Fusion |
|
|
AFS090 |
|
QN108
QN180
FG256 |
| AFS1500* |
* Current designs will be invalidated and must be re-compiled and re-run through Place & Route.
** Current designs will have routing invalidated and must be re-run through Place & Route.
Unless otherwise noted, these issues apply to all devices.
SmartGen
68324 – You can not create a symbol from a component generated by Smartgen v8.0.
This feature was available in previous versions of SmartGen and is a bug in Libero and Designer v8.0.
- Go to the Hierarchy Tab in the Design Explorer Window
- Switch from the Component View to the Module View => Right click and Create Symbol will be available, there but you still get an error if you try to generate a symbol
Workaround:
- Import as an 'HDL source' the HDL file generated with the component => Now the module is defined twice so pick its definition from the file located under <project>/hdl
- Right click on the selected HDL file and create the symbol
- You should not get the error message and the symbol is created
67731 – FlashPro error in programming due to duplicate region
names in FlashROM (A3P/E, AGL/e, AFS)
When using copy/paste in SmartGen FlashROM (FROM) interface to populate RAM contents, the cell name in Properties (e.g. Region_7-15) should change accordingly and properly reflect a unique region name. SmartGen may duplicate a region name using copy/paste. SmartGen allows this duplication of region names, but FlashPro will error during programming of the device.
Workaround: Region names must be unique. If a duplicate region name is created by SmartGen, manually change the "Name" under the Properties display.
67046 – SmartGen reports incorrect clock delay of 921 ps for
the delayed clock macro for IGLOO/e families when user selects hardwired
I/O as the input clock source. The correct delay is 470 ps.
This is fixed in v8.0 SP1.
65535 – SmartGen generated RTL behavioral model files are not shown in the Hierarchy tab.
These files are viewed in the “Other Files” category in the Files tab under components. To use the behavioral HDL model, import it into Libero IDE as user HDL.
Compile
66526 – Design fails to compile in v8.0 that previously compiled in v7.3 SP1 (AX Devices))
Layout
65422 – Layout incremental options must be explicitly set each time
SmartTime
65868/67289 – For APA and SXA devices, importing SDC with post compile or back-annotated netlist names on the buses reports an error. The workaround is to modify the SDC names to match the original netlist names.
66726/67295 – For the SXA family the Constraints checker incorrectly reports an error when a load constraint is set on a bus. This error can be ignored.
65525a/67296 – Correct Data Source for RTAX250S is "Silicon Verified". The SmartTime report includes if the Data Source is "Advanced", pre-silicon estimates, or "Silicon Verified", validated on silicon. For the RTAX250S, the Data Source incorrectly states "Advanced".
66042/67297 – The IOREG delay for IGLOO/e 1.2v devices always
shows 0 ns. This will be fixed in v8.0 SP1.
66064/67298 – Constraint checker incorrectly reports an error if output load value equals zero. Ignore this error. This does not affect delay calculation. 0 is a legal value for the output load and will be handled correctly.
65916/67300 – Clock names are not validated during SDC import. In SmartTime, if you enter a clock name with spaces an error is reported. However, when importing an SDC constraint with spaces in the clock name, there is no error check. The error is flagged later, when you open the constraint file.
65344/67301 - Min delay error messages during SDC import are misleading. The error message incorrectly reads "max" delay.
66404/67302 - SDC import allows clock constraint on a wrong pin or port (mismatched case). SDC import of clock constraints allows non-existing pins or ports to be clock sources. Any mismatch in names, including case, is accepted. The SDC reader in Libero/Designer v8.0 is now case-sensitive. The design will pass compile, and the timing report will report the constraint but the clock domain name will be missing for that particular pin/port.
66780/67303 – IGLOO/e IBIS export reports an error if the design
includes LVCMOS33.
Updated IGLOO/e IBIS models can be downloaded.
SmartPower
65525b – Correct Data Source for RTAX4000S is "Advanced". The SmartPower report includes if the Data Source is "Advanced", pre-silicon estimates, or "Silicon Verified", validated on silicon. For the RTAX4000S, the Data Source incorrectly states "Silicon Verified".
66549/67305 – For AGL030, "Typical" is the only valid selection in the Power Preferences Dialog.
Ignore other options.
Program File Generation
66622 – Security level may be incorrect and must be manually checked and corrected.
Exported TCL scripts will generate Medium security instead of HIGH security.
Workaround: Manually correct the exported script by replacing the one parameter '-security_level' with these 3:
'-fpga_security_level'
'-from_security_level'
'-efm_security_level'
A second problem occurs where the generated STP file is correct, but the ADB and PDB files incorrectly have Medium security level.
Workaround: Same as above. Manually correct the exported script by replacing the one parameter '-security_level' with the 3 listed.
Alternately, you can fix the security settings in the GUI.
Designer: Open ADB and reset security settings.
FlashPro: Load the PDB. Open FlashPoint and reset the security level.
This is fixed in Libero IDE/Designer v8.0 SP1.
66696 – Use PDB file for programming when Nonvolatile Memory (NVM Flash Memory) is used and CFI client is present. (Fusion/AFS devices)
When a Fusion device is programmed using a STAPL file that contains a CFI NVM client, programming will succeed, however, NVM verification will always fail. Programming Data Base (PDB) files are not affected by this issue. When using a PDB file, both programming and verification will work successfully.
FlashPro 6.0
66462 – Nonvolatile Memory (Embedded Flash Memory) cannot be modified in PDB files generated for M7AFS600
66326 – Do not change the name of the PDB (Programming Data Base) file created using Designer's FlashPoint.
Use different Designer Views to manage multiple programming files and different file names.
Device Support
66319 – PLL may not be used in AX2000-CQ256
Libero/Designer Linux or Solaris
62382 – On-Line Help browser requirements for Linux and Solaris OS:
Linux:
- Firefox 1.5 (2005)
- Mozilla 1.5 (2003)
Solaris:
64938 – Wind/U Startup Error Message
