Designer v7.2 Service Pack 1 Release Notes
(Oct 17, 2006)
Thank you for your interest in Actel's Designer physical implementation
software v7.2 SP1.
IGLOO Family
Support
Support for Actel's new IGLOO low power Flash FPGA family. The IGLOO
Flash*Freeze technology provides an ultra-low-power static mode that
retains SRAM and register information with rapid recovery to operation
mode. The mechanism allows you to enter and exit Flash*Freeze mode within
1 µS by activating the Flash*Freeze pin while all power supplies are
kept at their original values. In addition, inputs and input clocks can
still be driven or can be toggling without impact on power consumption.
The IGLOO device consumes as little as 5 µW in Flash*Freeze mode.
The SmartTime and SmartPower tools are updated to analyze the IGLOO
timing and power performance.
A Power
Calculator is separately available to determine the power dissipation
of your specific design.
The following IGLOO devices and packages are supported in SP1:
AGL600: FG256, FG484
AGL125: QN132, VQ100, FG144
AGLE600: FG256, FG484
Fusion Support
SmartGen Analog System Builder (ASB) enhancements for Fusion:
- The Sample Sequence Interface now provides a "Calculate Sequence" button
to automatically calculate the actual sampling rate. You can specify
the required sampling rate for a given input and adjust the sampling
sequence as necessary to meet the sampling rate requirements for each
of the sampled signals. The original manual flow is available by selecting "Allow
manual modification of operating sequence".
- The Real Time Counter user interface has been enhanced to provide
a "Configure Alarm Time" view. The Alarm Time view enables
you to enter the alarm time requirements in days, hours, minutes, seconds,
milliseconds, and microseconds. An alarm can be flagged to the Fusion
voltage regulator power supply monitor when the specified time is met.
The oscillator source can be an external crystal or an internal RC
network.
- The ASB voltage/current monitor input pair now provides a differential
voltage function. A differential amplifier measures the voltage drop
across the 2 inputs. The same pair in a different configuration can
measure voltage and current.
- The Memory System Builder User Interface includes a new Client option
to specify an external memory initialization file provided by Actel's CoreCFI
(Common Flash Interface) IP.
New
Die and/or Package Support
Fusion
ProASIC3 and M7 ProASIC3
- A3P060 QFN132
- A3P125 QFN132
- A3P250 QFN132
- M7A3P400 FG144, FG256, FG484, PQ208
ProASICPLUS Mil Temp
- APA1000 FG896 is now available in Mil Temp
AX/RTAX-S
RCLK Skew Modification
- Designer's Placement tool now imposes a load limit on the routed
clock (CLK) tracks when they are used for clock signals. The limit
is 16 loads for each half-tile row. A half-tile row is the series of
R-cells, C-cells, memory, and I/O modules (if applicable) occupying
one-half of the width of a core tile. Note that in a standard core
tile there are only 12 R-cells per half-tile row (AX250 and RTAX250S
only – 8 R-cells per half-tile row). The limit of 16 loads can
be exceeded only if a combination of R-cells and other loads (C-cells,
memory, and I/Os) are connected to the same CLK net.
- SmartTime is extending its timing model to account for routed CLK
tracks with loads > 16. This is needed to screen setup & hold
violations on existing designs with high loading situations, and
for non-clock signals on new designs.
- Additional warnings are provided when you open an ADB file. If
the warnings shown below are indicated, run SmartTime to see if critical
paths were affected.
- Clock signals:
The limit on track loading for routed clock nets is not met for
clock net %netName. The placement violates the limit of 16 pins
per track. It is recommended that you run layout in the non-incremental
mode to repair the problem.
- Non-clock signals:
Routed clock net %netName has high loading on some clock tracks.
Earlier versions of the SmartTime database had optimistic delays
for highly-loaded tracks. It is recommended that you use SmartTime
to verify that your design meets your timing constraints according
to the updated delay values.
Program File
Generation
- STAPL program file generation is enabled for the A3P125 ProASIC3
device.
SmartGen Static and
Dynamic PLL External Feedback Enabled
ProASIC3 external feedback is enabled for both static and dynamic
PLL. In order to implement this feature using the A3P250 and A3P1000
devices, you must order these devices with an "X" as part of
the part number, such as: A3P250-FGG144X60.
Note: SmartGen incorrectly provides a warning
when using A3P060, A3P125, and A3P400 devices. The previous External
Feedback issue has been fixed on these 3 devices. This warning is valid
only for A3P250 and A3P1000 devices.
SmartTime
Clock Removal/Recovery Checks are Enabled by Default
SmartTime now performs recovery and removal checks for asynchronous
inputs. These were available in Libero 7.2, but were turned off by default.
In 7.2 SP1, these checks have been turned on by default. This has been
done because timing violations due to Recovery/Removal timing should
be made known to the designer. Timing violations on asynchronous signals
may affect maximum frequency performance. As such, Recovery/Removal requirements
need to be taken into account during back-end implementation and analysis.
Users who wish to disable these checks can do so by un-checking the checkbox
under Tools => Options => General => "Enable Recovery and
Removal Checks" in SmartTime.
SmartTime
ProASIC3 and Fusion Timing Data Updates
- The Fusion Flash Memory Clock Minimum Pulse Width has been updated
from 5 ns to 4 ns
- FIFO WEN and REN setup times measured on ProASIC3 and Fusion silicon
were found to be larger than originally specified. SmartTime has been
updated to report the new setup times. See details below in Known
Issue 57825.
- The IO input delay step measured on ProASIC3 and Fusion silicon was
found to be larger than originally specified. SmartTime has been updated
to report the new delay.
- In ProASIC3 and Fusion silicon, multi-tile flip-flop and latches
now incorporate a more accurate software model. As such, their delays
are now somewhat longer than before. SmartTime has been updated to
report the new delay.
SmartTime
SX-A Timing
Since Designer version
6.2 SP1, for SX-A, eX, and RTSX-S/U FPGAs, a buffer may be automatically
inserted between logically adjacent flip-flops in Designer to minimize
the potential for hold violations. A direct connect route is used to
connect to the inserted buffer, but SmartTime ignored this net during
delay computation. This issue has been fixed in 7.2 SP1. Therefore,
paths containing logically adjacent flip-flops with automatic buffer
insertion will have slightly longer delays in 7.2 SP1.
SmartPower
Enhancements
- SmartPower now accounts for output load in the I/O power module for
the Fusion AFS600
- The SmartPower report generation UI provides better control over
the power report content.
- The SmartPower report structure makes it easier to read and locate
information in the report.
- The SmartPower report may now be exported in Comma Separated Values
(CSV) format for Excel spreadsheet analysis
- For ProASIC3 and IGLOO families, The Static power consumption
of I/O Banks is reported by SmartPower. You can find the reported values
as part of the breakdown in the Summary and Analysis tabs.
- Provides the following power modes for IGLOO and ProASIC3:
| |
IGLOO |
IGLOOe |
ProASIC3 |
ProASIC3E |
| Active |
 |
|
|
|
| Static - IDLE |
|
|
|
|
| Flash*Freeze |
|
|
|
|
| Sleep |
|
|
|
|
| Shutdown |
|
|
|
|
User Guide Updates
The following User Guides have been updated for SP1 and are only available
online. This Service Pack does not update these user guides in the Libero
v7.2 HELP "Reference Manuals" list.
Designer v7.2 SP1 requires a current Designer v6.0 or newer license.
IGLOO features, devices, and packages not
available in SP1
- Program file generation
- In System Programming (ISP) and Security Programming
- IGLOO devices in Synplify/Pro AE. Use equivalent ProASIC3 devices
using Synplify 8.5f.
- PALACE Physical Synthesis
ViewDraw Templates
59086 - Viewdraw.ini templates for stand-alone ViewDraw are
missing
For stand-alone ViewDraw use (not Actel Edition), a Viewdraw.ini file
is provided as a template with paths to ACTEL libraries under $ALSDIR/lib/wv/
directory.
In 7.2SP1:
-> Viewdraw.ini is missing under ProASIC3E directory on Solaris/Linux;
-> Viewdraw.ini is missing under IGLOO/E on Windows
-> Viewdraw.ini contents are incorrect under IGLOO on Linux
Contact Tech@Actel.com for access
to these missing templates.
Designer Device and I/O Selection
58719 – Compile will error out when you
change the package of an IGLOO design.
An example is:
- Create a new design for IGLOO AGL600-FG256 package.
- Declare sel[1] to be the FF pin and select "Compile".
- From the device selection wizard select FG484 for the AGL600 and "Compile" again.
- Designer will produce this error message:
"PDCF4:set_io for port sel[1] is not valid. You can place this
I/O with the option 'flash_freeze' only on the spec"
This error is confusing as no layout has been done. There should be
no conflicting placement from previous flow, and there should be no error.
The work around is to re-import the netlist and PDC.
59251 – Changing the I/O Selection in Designer's Device
Selection Wizard has no effect (All Families)
If you change the Default I/O Standard from the Device Selection Wizard
in Designer, the new selected I/O Standard is not fully propagated into
the design. Note that the actual applied values always can be verified
by using the Pin Report from Designer or the I/O Attribute Editor in
MultiView Navigator (MVN). To ensure that the desired I/O Standard technology
is used for your I/Os, you can use one of the two workarounds:
- After changing the Default I/O Standard in the Device Selection Wizard,
please recompile your design for the changes to take effect.
- Use a PDC constraint file or use the I/O Attribute Editor in MVN
to set the technology.
MultiView Navigator
58964 – ChipPlanner
Internal Error: Assertion Failed (ProASICPLUS)
Layout
59186 – Layout Runtime Increase on M7 Designs
V7.2 SP1 introduces Timing Driven Routing for ARM M7A3P/E designs. ARM
designs may experience an increase in layout runtime. This is expected
in SP1. Reductions in layout runtime will occur in subsequent releases.
58965 – APA
PLL must be connected to global resources (ProASICPLUS)
SmartGen
59047/58829 – Broken Hyperlink to Online Help
Using the Voltage Monitor or Crystal Oscillator User Interfaces in the
Fusion family Analog System Builder, you may find that a Tool Tip on
an Information icon has a broken hyperlink to Online Help. This bug will
be fixed in a future release.
58966 – SmartGen
does not refresh after a core is deleted from Libero
SmartPower
58967 – SmartPower
shows a power contribution of zero for OTB33PH Tristate buffer in
ProASICPLUS devices
SmartTime/ Timing Updates
57825 – Timing update
for ProASIC3 FIFO
FIFO WEN and REN setup times measured on ProASIC3 and Fusion silicon
were found to be larger than originally specified. For worst commercial-case
conditions, and for a -2 speed grade, REN setup-time is now 1.37 ns,
and WEN setup time is 0.94 ns. Users of the FIFO in ProASIC3 devices
with tight timing margin in their designs may need to check for timing
violations based on this new data. This specific timing applies to the
A3P250 and A3P1000 devices that are orderable with the "X"as
part of the part number, such as A3P250-FGG144X60. For timing information
on older existing material, please refer to A3P250,
A3P1000, and M7A3P1000 errata information.
58322 – FIFO Almost-Full and Almost-Empty propagation
delays larger than specified. (Fusion and A3P/E)
ProASIC3/E and Fusion FIFO AEMPTY (almost-empty) and AFULL (almost-full)
flags fail to assert at the correct cycle.
New silicon characterization data has shown larger AEMPTY assertion
delays with respect to RCLK, and larger AFULL assertion delays with respect
to WCLK. As a result, at high frequencies, the FIFO AEMPTY and AFULL
flags would fail to assert at the correct cycle.
Solution/Workaround: You can control the problem
by latching the AFULL and AEMPTY flags as close as possible to the FIFO
output.
59649 - Slacks reported in the min analysis violation report
are different from those reported in the min analysis timing report. (All
Families)
The slacks shown in the SmartTime Minimum Delay Analysis window match
those shown in the timing report and are correct. The slack reported
in the violations report for in-to-reg should not be used.
Program File Generation
58963 – Programming
fails with exit 11 (security failure). (ProASICPLUS)
