SmartGen
Fusion Support
- A new Analog System Builder (ASB) Sample Sequencer user interface
enables you to easily program the sequencer to jump to any analog input
in any order. A "Procedures" function enables you to set
up groups of unique sequences, such as power up, run, and power down.
- The ASB Temperature Monitor Block strobe timing has been updated
to improve temperature measurement accuracy.
- Tool tips in the Analog System Builder provide "point and view" brief
descriptions of features and links to online help.
- Core State Management and propagation to Libero IDE File Manager:
Smartgen detects changes in dependent cores and identifies which cores
in the workspace need to be updated. The Libero IDE File Manager shows
all cores that need updating. Resolving and updating all dependencies
is a one-click operation.
Fusion and ProASIC3
- BusLVDS and ULSICC * macros are
available
Fusion, ProASIC3, and Axcelerator Support
- A SmartGen Visual Configurator is now available for Two Port and
Dual Port RAMs, enabling you to easily identify and set the required
parameters.
- A SmartGen soft FIFO Controller with visual configurator is available.
SmartTime Advanced Clock
Analysis, New Datasheet Reports, and more
- SmartTime can now perform checks on asynchronous pins (i.e., Recovery
and Removal checks) By default, these new checks have been turned off
in Libero v7.2. This has been done so you will see no timing discrepancies
for your designs between v7.2 and prior Libero versions. You should use
these checks to characterize fmax performance on current designs.
- When setting a multi-cycle path, you can specify whether it applies
to setup check, hold check, or both
- Clock source latency can now be specified in SmartTime. Clock Source
Latency (also called insertion delay) is the time it takes a clock to
propagate from its origin to the clock definition point in the design.
It can be used to model off-chip latency when clock generation is not
part of the design. Clock Source latency can be specified in v7.2 either
in the SmartTime Constraints Editor or by using the set_clock_latency
SDC command.
- The Clock Source Latency window also enables you to analyze design
performance for clock “jitter” by specifying 'early' and 'late' times
for the rising and falling edges.
- An expanded parallel paths feature allows you to view and analyze parallel
configurations of a violating path in the expanded path window
- SmartTime v7.2 can create "datasheet" reports that provide
detailed information about the pins, I/O technologies, and timing properties
in your design
- New TCL commands are available: st_create_set, st_remove_set, st_edit_set,
st_commit, st_restore, st_set_options, st_list_paths, st_expand_path
- The Clock Control Circuitry delay step has been updated from 160ps
to 200ps (typical condition) in the SmartTime delay calculator to more
adequately reflect delays found in the silicon (Fusion and A3P)
- DDR macro delays have been updated and incorporated to balance rising
and falling clock-to-out times and improve the high-frequency performance
of the designs (Fusion and A3P)
- HCLKBUF / RCLKBUF delays have been updated to reflect characterization
data from the RTAX4000S silicon
SmartPower Advanced Power
Analysis Features
- You can now view power by component type, component instance, and voltage
rail.
- Advanced power analysis can now be performed for I/O pins based on
their output load, slew rate, and output drive strength.
- A new Enable Rate feature allows you to specify the percent of time
each bidirectional or tri-state I/O actively drives a load; SmartPower
will calculate I/O power dissipated based on that information.
- The power tables displayed in the Summary and Analysis windows can
now be customized by right-clicking on them.
Fusion and ProASIC3
Placement Enhancement Provides 8% Performance Improvement
- Layout improvements for Fusion and ProASIC3 provide 8% performance
improvement on average.
- A fast placement improver has been added to focus on timing optimization
of critical paths.
- Timing-driven routing further optimizes the performance while balancing
congestion.
- Placement timing models were adjusted to improve I/O setup delays.
MultiView Navigator (MVN) Enhancements
- Global nets can be automatically placed using the Global Planner function
within the MVN tools
- The Global Planner has been enhanced to distinguish between Locked
and not Locked Quadrant Clock regions. Each Quadrant Clock region can
now be marked as locked. New capabilities are:
- Each Quadrant Clock region can be locked manually using a PDC file
or through the MVN
- Each locked Quadrant Clock region is not changed, while other Quadrant
Clock regions are deleted and recreated each time the Global Planner
is executed
Incremental Automatic I/O
Bank Assigner for Axcelerator, ProASIC3 and Fusion
- The I/O Bank Assigner has been enhanced to distinguish between user
and tool assigned I/O Banks. Each I/O Bank can now be marked as locked.
New capabilities are:
- I/O Banks can be locked manually using a PDC file or through the
MultiView Navigator (MVN)
- Each locked I/O Bank is not changed, while other I/O Banks are
reassigned each time the I/O Bank Assigner is executed
- If Incremental Layout is selected, all pre-assigned I/O Banks are
treated as locked
Designer "Views" Enhancement
in Libero IDE
- Multiple ADBs (Designer implementations or "Views") are now
available on the Designer Place-and-Route button via a dropdown menu.
A Designer Views category is also visible in the Project Manager File
Manager. This replaces the previous "Implementations" interface
in Libero.
Other New Fusion Support
- Dynamic Clock Conditioning Circuitry (CCC) support enables you to dynamically
change the CCC configuration by entering the control data via the JTAG
interface
- Flashpoint allows you to set security levels and extend them to the
Flash Memory System Builder blocks, protecting Flash Memory System Builder
blocks from erroneous JTAG read/write commands
- AFS1500 in the FG256 package
A3P400 Package
Update
- All existing designs using A3P400-FG256, FG484, and PQ208 devices must
be re-compiled to utilize updated package information. Libero
IDE/Designer v7.2 will invalidate designs using these packages and put
them back into a pre-compile state. Existing physical constraints will
be invalidated. (A3P400)
Other Designer Features
- Post-Compile netlist export is now enabled for ProASICPLUS and
A54SX-A devices
Axcelerator and RTAX-S
RAM Updates
ProASICPLUS Phase
Lock Loop (PLL) and Clock Conditioning Circuit (CCC) Specification Changes
ProASICPLUS Unused
I/O Change
- In release v6.1, the ProASICPLUS routing would balance
the loads on clock lines in and around the RAM rows. For this purpose,
routing may have employed the Output-enable input of an unused I/O, which
resulted in the I/O pin being displaced from its expected weak-high state.
This may be a problem in designs where the unused I/O pin was being driven
from the board to a state in conflict with that of the Output-data.
- Release v7.2 fixes this problem by avoiding the Output-enable pins
for load balancing purposes. In existing designs, you should run Incremental
routing, verify timing, and generate the programming file. Performance
impact is negligible.
Device/Packages
Availability
- AFS1500 FG256 is available
- A3P400 FG144 is available
PALACE AE 3.3
56555 – PALACE 3.3 physical synthesis does not
support the AFS1500 device.
MultiView Navigator
56096 – Refresh issue when QCLK region deleted
through LCA. When you go to the Nets tab in the MultiView Navigator
and select a global net and then run Local Clock Assignment on it, a
region is created as expected.
SmartTime/Timing
54291/56077 – The "st_list_paths" TCL
Command Ignores the Number of Paths Set (All Families)
55820 – Violation
is reported when the slack is 0 (All Families)
54900 – Designer
crashes when executing a script with the st_restore command (All
Families)
54287/55856 – Generated
clock constraint is not honored after clock constraint been removed then
added back (Fusion)
54290/55833 – FIFO
Empty Flag Failing to De-Assert at Correct Time (Fusion, A3P/E)
AX/Timing
56392/56508 – FIFO
setup time fix has impact on performance based on FIFO depths. (Axcelerator,
RTAX-S)
Axcelerator designs including embedded FIFOs may see a performance degradation
using Libero IDE/Designer v7.2. A change was made in v7.2 to correct the
Read and Write Enables with respect to the read and write clock. Setup
times have been adjusted incrementally based on FIFO depth. We recommend
that you run timing analysis to verify if the timing requirements are still
met after using Designer v7.2.
51587/54289 – AX
FIFO Empty Flag Failing to De-Assert at Correct Time (Axcelerator,
RTAX-S)
CoreMP7
54292/55858 – ModelSim not
Loading CoreMP7 Bus Functional Model (Fusion M7AFS, M7A3P/E)
54293/54821 – CoreMP7
Designs with New UFROM Cannot be Placed in Designer. (Fusion M7AFS,
M7A3P/E)
54181 – CoreMP7 VHDL Support Changes have been
made in the Post-Synthesis VHDL Export of CoreMP7 Designs. Previously,
a double entity declaration existed of the A7S module (once in the a7sBFM_TS_fusion.vhd
and again in the VHD file generated by Synplicity), which caused the
following error in ModelSim:
"# ** Error: (vsim-13) Recompile ../simulation/postsynth.YourTopLevelEntity
(def_arch) because ../simulation/postsynth.a7s has changed."
Comment the two lines below to change the architecture binding for the
entity A7S in the generated VHDL file which direct ModelSim to
use the architecture found in the a7sBFM_TS_fusion.vhd file:
-- for all : A7S
-- use entity work.A7S(DEF_ARCH);
SmartGen
56518 – Error generated when setting Dynamic
CCC (DYNCCC) using ClkA = 99 and Primary Frequency = 100. This
is only a problem using Dynamic CCC. Static CCC setup using the same
parameters functions properly. (A3P/E)
55550 – Analog System Builder Sample Sequencer
v7.2 Enhancement Issue for previous designs (Fusion).
Sample Sequences generated prior to v7.2 should be terminated with a jump
in 7.2. This is not a v7.2 issue, this is a requirement for designs created
prior to v7.2 that will also use v7.2
In the 7.2 Sequencer, the concept of "Procedures" has been added
to the Sample Sequencer User interface. A “Procedure” defines a set of
sequences and is independent from other Procedures. Procedure sequences
should terminate with a 'terminating' operation such as JUMP, STOP, or
POWERDOWN. A check is performed to ensure that a Procedure does not over-run
into another unrelated Procedure.
Previous versions of the SmartGen Analog System Builder (prior to v7.2)
allowed a sequence to be created w/o a terminating operation. Pre 7.2 generated
cores that have sequences that end in a non-terminating operation when
imported into the 7.2 release of the Analog System Builder will require
modification if the core is to be regenerated. If you do not need to regenerate
the core, you can use the core as is without harm.
Voltage and Current Inputs:
Pre 7.2 generated cores only use 10 time slots to sample the voltage and
current inputs, and do not use the Jump operation. If an existing design
includes the voltage and current measurement functions in the Analog
System Builder, the cores should be regenerated using v7.2 to be compliant.
(Fusion)
56413 – On Demand Save and Read Pipeline combination
is an invalid configuration. When using the "Enable On
Demand Save to Flash Memory" function in configuring RAM in a Fusion
design, the “Read Pipeline” function should not be used. Do not check
the “Read Pipeline” checkbox. The Read Pipeline function is not intended
for use in combination with Enable On Demand Save. (Fusion)
Axcelerator RAM Models
46209 – Axcelerator RAM Models, simultaneous
reading and writing of AX RAM to the same address. Prior to
v7.2, this would result in an indeterminate value being read from the
address, depending on the internal timing between the two operations
during that cycle. In v7.2, AX and RTAX-S simulation models were changed
to detect a read/write address match and to create a time slot around
the positive edge of WCLK/RCLK so that simultaneous read/write to the
same address will result in Read Data being driven to "X" after
one clock cycle.
Designer
54288/56155 – Designer/Smartgen
doesn't launch on a Linux 4.0 license server machine
55933 – Designer .adb implementation file not
showing in the Designer Place & Route box on the Libero IDE Design
Flow window. Under some circumstances after creating additional
Designer Views, the implementation .adb file is not visible in the drop
down box available on the Designer Place & Route button on the Libero
IDE Design Flow window. The implementation view .adb file however is
visible in the Libero IDE File Manager.
Workaround: Open the Designer .adb from the
File Manager and re-save.
56564 – IBIS support is not available for Fusion
devices. IBIS support will be available for Fusion devices in
a future release.
