Designer v7.1 Release Notes
(Apr 5, 2006)
Thank you for your interest in Actel's Designer physical implementation
software v7.1.
- ARM-Enabled Fusion
Actel Fusion is the world's first mixed-signal FPGA, integrating configurable analog,
large Flash memory blocks, comprehensive clock generation and management
circuitry, and high performance programmable logic in a monolithic
device.
The innovative Actel Fusion architecture can now be used with Actel soft
ARM7 (CoreMP7) and 8051
(Core8051) cores and is the definitive mixed-signal
platform.
Libero IDE v7.1 introduces design support for the ARM-Enabled Fusion
M7AFS600.
| Device/Die |
Packages |
Speed Grade |
| M7AFS600 |
PQ208 |
Std, -1, -2 |
| M7AFS600 |
FG256 |
Std, -1, -2 |
| M7AFS600 |
FG484 |
Std, -1, -2 |
Note: CoreConsole v1.1 is required
for M7AFS ARM7/Core MP7 subsystem design.
- Fusion Die and Package Support
| Device/Die |
Packages |
Speed Grade |
| AFS090 |
QN108 |
Std, -1, -2 |
| AFS090 |
QN180 |
Std, -1, -2 |
| AFS090 |
FG256 |
Std, -1, -2 |
| AFS250 |
QN180 |
Std, -1, -2 |
- Axcelerator Die and Package Support
| Device/Die |
Packages |
Speed Grade |
| AX2000 |
CQ256 |
Std, -1 |
- ProASIC3 Package Updates
The following packages have been updated for the respective ProASIC3
dies. Libero IDE/Designer v7.1 will invalidate all existing ADB files
and move the design back to a pre-compiled state. You must manually
save existing design constraints prior to the invalidation by exporting
from the current ADB to a separate file, and then re-importing after
the invalidation has occurred.
Device: A3P125 VQ100
There are no changes in the device pin-outs. There are changes in the
die probe pads (used for die testing) that necessitated a package
update.
Device: A3P060-VQ100
Changes include:
Globals were shifted:
From 43 to 44
From 44 to 45
From 45 to 46
Second VMV1 added on pin 50
Global added on pin 60
Total number of I/Os remain unchanged
| Pin # |
Old Pin Name |
| 43 |
GDC2/IO57RSB1 |
| 44 |
GDB2/IO56RSB1 |
| 45 |
GDA2/IO55RSB1 |
| 46 |
IO54RSB1 |
| 50 |
NC |
| 60 |
IO44RSB0 |
| Pin # |
New Name |
| 43 |
IO57RSB1 |
| 44 |
GDC2/IO56RSB1 |
| 45 |
GDB2/IO55RSB1 |
| 46 |
GDA2/IO54RSB1 |
| 50 |
VMV1 |
| 60 |
GCC2/IO43RSB0 |
Device: A3P060-TQ144
Changes include:
Globals were shifted:
From 61 to 65
From 65 to 66
From 66 to 67
Total number of I/Os remain unchanged
| Pin # |
Old Pin Name |
| 61 |
GDC2/IO57RSB1 |
| 65 |
GDB2/IO56RSB1 |
| 66 |
GDA2/IO55RSB1 |
| 67 |
IO54RSB1 |
| Pin # |
New Name |
| 61 |
IO57RSB1 |
| 65 |
GDC2/IO56RSB1 |
| 66 |
GDB2/IO55RSB1 |
| 67 |
GDA2/IO54RSB1 |
Device: A3P060-FG144
Changes include:
Globals were shifted: Shift in I/O numbers
Total number of I/Os remain unchanged
| Pin # |
Old Pin Name |
| K9 |
GDC2/IO57RSB1 |
| H8 |
GDB2/IO56RSB1 |
| J9 |
GDA2/IO55RSB1 |
| K8 |
IO54RSB1 |
| Pin # |
New Name |
| K9 |
GDC2/IO56RSB1 |
| H8 |
GDB2/IO55RSB1 |
| J9 |
GDA2/IO54RSB1 |
| K8 |
IO57RSB1 |
- Automatic I/O Bank Assigner Enhancements for Fusion, A3P,
and Axcelerator
The Automatic I/O Bank Assigner has been enhanced to successfully
resolve more complex I/O technology assignments.
- Additional LVCMOS I/O Support for Axcelerator
LVCMOS 2.5 V now offers 24mA output with a 4x drive strength, replacing
the previous 12mA with 4x drive strength. 12mA output is now available
with a 2x drive strength. If you have an existing design and it includes
LVCMOS 2.5V 12mA outputs based on a 4x drive strength, in order to
keep the 12mA output you must re-select the output using a 2x drive
strength. If you do not change the drive strength to 2x, the output
will be 24mA.
Designer v7.1 requires a current Designer v6.0 or newer license.
Designer
53764 - For Actel ProASIC3E and Fusion families, the
I/O standards SSTL 2.5v (Class I & II) and SSTL 3.3v (Class I & II),
drive strengths have been reduced based on silicon measurements. Note that
these updated drive values still meet all JEDEC SSTL IOH and IOL requirements.
The 7.1 release of Designer has not been updated with this information;
it is planned to be updated in the 7.2 release. Output drive strengths
as represented in version 7.1 (“Estimated") and in version 7.2 (“Updated”)
are shown in the following table:
| |
Output Drive Strength Specification |
| Estimated |
Updated |
| SSTL 2.5V - Class I |
17 mA |
15 mA |
| SSTL 2.5V - Class II |
21 mA |
18 mA |
| SSTL 3.3V - Class I |
16 mA |
14 mA |
| SSTL 3.3V - Class II |
24 mA |
21 mA |
The Fusion datasheet
has been updated with the latest information. ProASIC3E datasheet will
be updated by 4/30/2006. Please refer to them for further details.
Fusion
53411 - Designer v7.1 will invalidate Fusion AFS250
ADBs created in Designer v7.0 SP1 THAT USE THE MEMORY SYSTEM BUILDER. All
designs will be set back to the pre-compile state to correct a connectivity
mismatch in the Flash Memory Builder I/Os. You can save your layout and
constraints by using the Layout "Fixed" option and the "Keep Existing" Physical
Constraints check box ON in the Compile menu.
41646 - Cross-probing
a path from ChipPlanner to NetList Viewer function is not functional
SmartGen
50657 - Memory System Builder will quit when you rapidly
click on the Start Address up/down arrow on Solaris and Linux OS. This
feature has been turned off on Solaris and Linux in v7.1.
54003 - Running
SmartGen On RedHat Linux Enterprise 3.0
54647 - In a Fusion design, SmartGen generates an incorrect
direction for port USER_DOUT for data storage clients in FlashMemory System.
This affects systems WITH ONE OR MORE DATA STORAGE CLIENTS. In this case
the OUTPUT port USER_DOUT is reversed as INPUT.
Workaround:
Verilog and VHDL Users:
- Change the direction of USER_DOUT as out in the top-level entity/module.
This step is the only change needed for Verilog.
VHDL users follow this additional step:
- Reverse the signal Assignment in the body just after BEGIN where
DOUT gets assigned to signal
In the case of designs with data storage + one or more AS, init or RAM
clients
change
\USER_DOUT_TO_net[31]_net_1\ <= USER_DOUT(31);
to
USER_DOUT(31) <= \USER_DOUT_TO_net[31]_net_1\;
In the case of designs with data storage clients only
change
\NVM_DAT_FROM_net[31]_net_1\ <= USER_DOUT(31);
to
USER_DOUT(31) <= \NVM_DAT_FROM_net[31]_net_1\;
Change all the DOUT assignments in this manner.
For AFS090, DOUT is only 16 bits wide. For all other devices DOUT is
32 bits wide.
SmartTime
52021 - SmartTime
does not honor False Path on ACM
51939 - SmartTime
Crashes When Creating a Generated Clock Constraint
