Designer v7.0 Release Notes
(updated on Dec 13, 2005)
Thank you for your interest in Actel's Designer physical implementation
software v7.0.
Designer v7.0 introduces support for Actel's new Fusion: the world's first mixed-signal
FPGA, integrating configurable analog, large Flash memory blocks, comprehensive
clock generation and management circuitry, and high performance programmable
logic in a monolithic device. Designer v7.0 provides optimized place-and-route,
timing constraint/analysis, and power analysis for Fusion-based designs.
SmartGen Core Generator
SmartGen (previously ACTgen) is enhanced to support the generation and
configuration of Fusion peripherals, such as analog blocks, real time
counters, on-chip memories including RAM, and user FlashRom Memory (FROM).
Learn more about SmartGen
features for Fusion devices.
Fusion Device and Package Support
| Device/Die |
Packages |
Speed Grade |
| AFS600 |
208 PQFP |
Std, -1, -2 |
| AFS600 |
256 FBGA |
Std, -1, -2 |
| AFS600 |
484 FBGA |
Std, -1, -2 |
Programming Support for ProASIC3
STAPL programming file generation is now available for the A3P1000 device.
eX, SX, SX-A and RTSX-SU High Reliability Applications
This release includes a library enhancement (B-Antifuse Reduction -
BAR) which reduces the occurrence of nets with single-B antifuses. Designers
of high reliability applications targeting eX, SX, SX-A and RTSX-SU FPGAs
can reduce the occurrence of nets with single B-antifuses by an average
of 40% by repeating design compilation using the new library elements
in this release.
New Device Support in Libero Gold. The following devices
are now available using a Libero IDE Gold or Designer Gold license.
- Fusion AFS600
- ARM7 CoreMP7 M7A3P250, M7A3P1000, M7A3PE600
- ProASIC3 A3P600, A3P1000
- 51524 - Existing ADB netlists will be scanned for
improper PLL calculations in violation of a 1.5 - 5.5 MHz PLL input
core frequency rule. ADBs and netlists violating the rule will be invalidated
and you will be required to regenerate the PLL using SmartGen v7.0.
Invalidated designs should be re-synthesized, and re-run through standard
compile, place, and route.
- 51873 - Correction to the v7.0 Online Help: SmartGen
Dynamic Clock Conditioning Circuitry (CCC) for PLL generation is not
available in v7.0.
- Existing designs that contain FlashRom (FROM) cores will be invalidated
and must be re-compiled. The original A3P FlashROM core is asynchronous.
Under certain Vcc and temperature conditions, data read out of an existing
FlashROM core may not be accurate. The FROM core has been changed to
a synchronous design. A CLK pin and synchronization circuitry has been
added. Existing designs incorporating this core must have the netlist
regenerated using SmartGen v7.0, and run through standard synthesis,
compile, and place and route flows.
Designer v7.0 requires a current Designer v6.0 or newer license.
General
50994 - The Windows Designer.exe v7.0 can address more
than the normal 2 GB RAM per process. The Designer.exe has been built
so that a PC that is configured to allow more than 2 GB of RAM per process
can let Designer.exe take advantage of the extended addresses in memory.
This enables the Designer process to allocate more memory for larger
devices or projects.
System requirements:
Modify Windows XP Professional that has 4 GB RAM. Modify the Boot.ini
to enable large-address-aware Processes. See the following for more
information.
http://support.microsoft.com/default.aspx?scid=kb;en-us;q289022
http://support.microsoft.com/default.aspx?scid=kb;en-us;Q171793
SmartGen
51501 - Verilog generation of Fusion Analog and Nonvolatile
Memory (NVM) is not supported in v7.0. V7.0 supports VHDL only for Analog
System Builder (ASB) and NVM. Although the Libero Project Manager allows
you to set up your project selecting Verilog as your desired HDL, SmartGen
will not provide a Verilog output for these cores.
51806/51929 - SmartGen
PLL User Interface gives illegal configuration of divide by 0.5 (Fusion)
51729/51926 - Importing
an Analog Core for another project does not include the full netlist
(Fusion)
48242/51925 - The
threshold flags related to the un-sampled channels do not show up in
the Analog Block top level Netlist (Fusion)
51314/51923 - SmartGen
generates wrong netlist for 11x16 memory configuration (AX)
51990 - Regenerating a UFROM macro with a different
name may cause SmartGen to close. (ProASIC3/E). If you create a SmartgGen
workspace for an ProASIC3E UFROM macro, close it, and then re-open it
and try to give the same macro a different name, SmartGen may suddenly
close. Do not try to rename an existing UFROM Macro. Instead, delete
the original macro and create a new macro as needed.
50657 - Create Flash Memory System Builder interface
closes when you quickly click on the "Start Address" up arrow.
(Fusion, Solaris/Linux OS). After selecting, configuring, and closing
the "Add (Initialization, Data Storage, RAM Initialization) Client" dialogs,
with the "Create Flash Memory System Builder" menu still open,
rapid clicking the up arrow in the "Start Address" column will
cause the Create Flash Memory System Builder UI to suddenly close.
51369 - Fusion cores do not automatically show in the
list of "Configured Cores". In v7.0 the new cores are not visible
until after you close the "Create Core" dialog box and reopen
it. All cores are visible in the Configured Core View Window.
PALACE
50956 - Palace 3.1 does not support ARM7 CoreMP7 devices.
Do not use PALACE 3.1 to perform physical synthesis on CoreMP7 designs.
51845 - Palace 3.1 does not support Fusion AFS600 devices.
Designer Misc
51832 - Net names should not be differentiated by upper/lower
case only in RTL in AFS/A3P/A3PE. Although Synplify accepts and produces
a netlist including net names that are only different due to upper or
lower case in the name, (e.g. "up_data_in [4[" and "uP_data_in
[4["), Designer reads the net names in the netlist as duplicates
and returns an error.
Work-around: Do not use upper and lower case as a means for differentiating
net names.
51834/51927 - Designer
does not browse to the correct location for .efc file in Fusion programming
file generation stage (Fusion)
51685 - User FROM (FlashRom) encryption and programming
are not available in this release (M7 Devices)
51595-51823-51886 - The FG256 package for the M7A3P250
is not available in this release. Existing designs using the FG256 package
cannot be opened by Designer. You must select an alternate package.
SmartTime
50882/51922 - SmartTime
shows false violations for a path that does not exist (eX, ProASICPLUS,
RTSX-S, SX-A)
52021 - SmartTime
does not honor False Path on ACM (Fusion)
BSDL File Generation for M7 Devices
52147 - Generic and design specific BSDL file generarion
for ARM7 M7A3P250, M7A3P1000, and M7A3PE600 are incorrect. Please use
A3P/A3PE BSDL File generation temporarily.
BSDL File Generation for AFS600 Fusion
The AFS600 device in the PQ208 package has duplicate Vcc pins. The pin
map contains two pins labeled #112 and two pins labeled #45. To work-around
this problem, remove one pin #112 and one pin #45 from the pin list.
