Designer v6.3 Release Notes
(Nov 2, 2005)
Thank you for your interest in Actel's Designer physical implementation software
v6.3.
Design flow support for CoreMP7, Actel's FPGA optimized
soft IP ARM7 microprocessor core.
Creation of a CoreMP7 subsystem requires Libero IDE
software, CoreConsole software, and a
license, all available from
Actel. Please refer to the Libero
IDE v6.3 Release Notes for more information.
SmartTime
Enhanced Min_Delay (EMD) support — SmartTime now provides support for precise
minimum delay/hold-time analysis based on actual characterized silicon timing data.
This new feature eliminates the need to over-guardband a design for minimum delay,
providing a more comprehensive, precise way to perform chip-to-chip evaluation of
external setup/hold and clock-to-out timing. EMD supports AX, RTAX-S, and APA devices
in v6.3.
Generated Clocks in SmartTime 6.3 enable you to specify the output frequency of
a PLL based on arithmetic operations applied to a reference (input) frequency. Generated
clocks are supported for imported SDC constraints and can also be created within
SmartTime.
SmartTime can now check for minimum pulse widths on paths and use this information
to determine the maximum operating frequency of the design.
Automatic I/O Bank Assigner for ProASIC3 and Axcelerator
A new I/O Bank Assigner automates the process of assigning necessary voltages to
I/O banks and aggregating compatible I/Os to those banks based on the specifications
of the design. Pre-defined (manual) assignments are respected, and VREF pins are
assigned where required. The process is automatic when running layout in Designer,
but can be controlled in the MultiView Navigator with undo, redo, etc.
MultiView Navigator
New commands in the MultiView Navigator (MVN) help you perform several tasks with
one click: Commit and Check, Lock All, Unlock All, Unassign All from Location, and
Unassign All from Region. The command restructuring improves both the usability
and the responsiveness of the tool. This version also includes the ability to invoke
Automatic IO Bank Assignment from within MVN and adds support for SX-A and eX families
of Actel devices.
SmartPower
SmartPower now computes power for Worst Case/Best Case Operating conditions. SmartPower
applies a voltage derating for dynamic power and a temperature derating for static
power. Normally, higher voltage leads to higher dynamic power, and higher temperature
leads to higher static power. The new operating conditions can be set in the SmartPower
Preferences dialog.
Enhanced Memory Initialization flow for ProASICPLUS
now preserves the MEMORYFILE parameter through the design flow. ACTgen will create
RAMs with the parameter mapping automatically included for each RAM, with each instance
pointing to a unique memory file. ACTgen also creates template memory files for
all RAM instances, initialized to zeroes. Netlist import and export will preserve
the parameter, so that post-compile, post-layout and timing simulations are able
to use the .mem files created by ACTgen. The Synplify library (8.2b) includes the
parameter MEMORYFILE for all memory macros.
ChainBuilder
1.1 software now supports ProASIC3 devices.
ACTgen now includes access to Actel's Intellectual Property Catalog
that enables you to quickly view the complete list and detailed information on Actel's
Intellectual Property (IP) core offering.
- Existing designs with ADB files will be invalidated and must be re-routed. This
is to take advantage of enhancements in place-and-route. When opening an existing
ProASIC3 ADB file, a message instructs you to run incremental routing by checking
the "Route Incrementally" checkbox in the layout options box. The impact
on performance is minimal; identical performance is not guaranteed. (49951)
- Due to a package data update, Designer invalidates existing A3P1000 ADB files (created
in any pre-6.3 release) and returns to the pre-Compile state. TO KEEP YOUR EXISTING
PDC AND SDC CONSTRAINTS, EXPORT THEM USING V6.2 SP2 BEFORE RUNNING YOUR DESIGN IN
V6.3. IMPORT THE SAVED CONSTRAINTS BEFORE RUNNING RE-COMPILE IN V6.3. PREVIOUS LAYOUT
RESULTS CAN NOT BE GUARANTEED.(49953)
- Some PLL configurations created pre-v6.3 may be unstable. When an unstable configuration
is detected by Libero/Designer v6.3 during compile, an error message appears that
requires you to regenerate your PLL using ACTgen v6.3. Compile will not proceed
if this error message appears. After reconfiguring the PLL with v6.3, synthesize
the design, then run compile, and full place and route. (50170)
Designer v6.3 requires a current Designer v6.0 or newer license.
51000 — PALACE floating license daemon can not be started
when using Solaris 9. When launching PALACE with a floating license on a Solaris
9 system, FlexLM will show this error:
(aplus) Vendor daemon can't talk to lmgrd (Cannot read data from license server
(-16,287:22 "Invalid argument")
The PALACE daemon can not be started.
To solve this problem:
Do NOT start the lmgrd from the unix prompt directly. Instead, execute the Bourne
Shell script which is located in the Palace 3.1 Solaris release in/bin/run_lic.sh
This workaround is also published in the Macrovision Web Site: http://www.macrovision.com/support/by_catagory/FLEXlm_resolutions.shtml
The script is as follows:
#!/bin/sh
ulimit -n 1024
ulimit -H -n 1024
# please change the license directory and file name
./lmgrd -c /my_dir/my_lic.lic
I/O Bank Assigner
50934 - Layout may fail if I/O technologies have been changed or
added after the I/O Banks have been assigned through Layout or the I/O Bank Assigner
in MVN. You may need to unassign a sufficient number of I/O Banks for the I/O Bank
Assigner to find a feasible solution. In this event, you will be directed to Online
Help to view actions that can be taken to solve the failure.
MultiView Navigator
48357 - Designer
loses an MVN constraint when migrating an A3P design from v6.1 to v6.2
ACTgen
50516 - ACTgen IP catalog FTP access hangs. IP catalog access in
ACTgen from a remote location (such as home) can "hang" for several minutes.
The long delay occurs in one of the FTP functions. If this occurs you can wait several
minutes for the hang to clear, or, turn off the software update check in the Libero/Designer
preferences, or IP Update in ACTgen.
Timer/SmartTime
47402 - Timing
violation report is empty when the inter-domain analysis is turned on (all devices)
