Designer v6.2 Service Pack 2 (SP2) Release Notes
(updated Sep 8, 2005)
Thank you for your interest in Actel's Designer FPGA physical implementation
software. These release notes outline various updates in the v6.2 SP2
software.
- RTAX4000S Support. This release introduces support for the new RTAX4000S
device. Synplify 8.2, available directly from Synplicity at http://www.synplicity.com/downloads/download1.html provides
synthesis support for this device. Alternatively, Libero IDE v6.2/Synplify
AE 8.1a users can synthesize the device by selecting RTAX2000S or AX2000
in the Synplify 8.1a GUI. For complex designs, Layout Effort Level
5 is recommended. Programming file generation is not supported at this
time.
- Packages Supported
- 352 CQFP; Std & -1 Speeds
- 1272 CCGA/LGA; Std & -1 Speeds
- IBIS model generation and export for Axcelerator and RTAXS devices.
Signal names and corresponding pin numbers, type of package, and I/O
standard information are automatically consolidated and exported in
a file upon selecting File Export > Other Files > IBIS.
- You can now generate a Global Net Report for ProASIC3 designs.
This report documents:
- loads of the clock nets
- shared instances information
- automatic global net assignments made by Layout
This information is helpful if Layout fails to find a global net assignment
solution. After Layout is complete, from the Tools menu in Designer
select Reports to generate the "GlobalNet" report . This Global Net
Report is only available for designs created with v6.2 SP2. This report
cannot be generated from ADB files created on releases prior to v6.2
SP2.
- Routing improvements have been made for ProASICPLUS devices,
resulting in a 3% average performance improvement.
- When starting program file generation for the A3PE600ES, you must
use one of the following options for unused I/Os:
- Tie off each unused I/O with a pull-down resistor (for low current)
-or-
- Tie off each unused I/O with a pull-up resistor.
Selecting the pull-down option will reduce the current on ES devices.
Users migrating from ProASIC PLUS must select the pull-up
option to maintain compatibility with the APA architecture. The pull-up
option is pre-selected as default.
- Mixed mode I/O support has been removed from APA devices. As of SP2,
use of any of these mixed mode I/Os is prohibited: OB25XX, IOB25XX,
IOBL25XX, OTB25XX, OTBL25XX, or IB25XX. If any of these I/Os are detected
in an existing ADB, an error message appears, and alternative non mixed-mode
I/Os are suggested.
- CLKINT cell delay on ProASIC3 devices has been updated based on
new data. There may be a small performance change.
Designer v6.2 SP2 requires a current Designer v6.0 or newer license.
48132 - In the Multiview Navigator, the "Active List
Help" link is broken in the Tools -> Active List -> Clock Nets -> Active
List Help selection.
48919 - A3P/E post compile pre layout Local Clock Assignment
(LCA) report will be blank for designs created prior to v6.2 SP2. The
LCA Global Net report currently can only be used with designs created
with v6.2 SP2.
49339 - Smartpower shows a zero value static power
for the RTAX4000S. Power information for this device is not yet available.
