Designer v6.2 Release Notes

(Jul 2005)

Thank you for your interest in Actel's Designer FPGA physical implementation software. These release notes outline various updates in the v6.2 software.

What's New in this Release
Important Notices
Licensing
Resolved Issues
New Known Issues and Workarounds
Previous Known Issues and Workarounds
Download and Install Designer v6.2

SmartTime Timing Environment enables you to perform detailed timing analysis and quickly determine the steps necessary to achieve design closure. The SmartTime environment incorporates multiple "views" as follows:

The SmartTime Constraints Editor view enables you to list, edit and create precise timing constraints. It includes a graphical user interface with visual dialogs that help you meet your timing requirements.
The SmartTime Analyzer view simplifies the analysis process by enabling you to track paths with timing violations and identify critical paths. You can then set specific timing constraints or exceptions on the violating paths to tighten or relax the requirements and quickly iterate toward timing closure.
The SmartTime Timing Analyzer view enables you to manage multiple clock domains, perform timing analysis and identify timing violations across synchronous or asynchronous clock domains.
SmartTime also supports the SDC (Synopsys Design Constraints) flow. To learn more, read the SmartTime Tutorial.
SmartTime includes detailed and user-customizable timing reports.
SmartTime supports ProASIC3, ProASIC3E, ProASIC^PLUS, ProASIC, SX-A, RTAX, RTAX-S, and eX devices.

Designer Enhancements

MultiView Navigator

Provides cross-probing between SmartTime and ChipPlanner. After place-and-route you can select a critical path in SmartTime and observe the logic path and direction of the signal path in ChipPlanner. This feature makes it easy to select a path and identify the relative location of the logic that makes up the path.
Includes a new "Package Pins Tab" in the I/O Attribute editor that lists all pins in a targeted package, along with the I/O attributes and I/O banks. This makes it easier to assign address/data ports to adjacent pins and assign or view Vref pins.
Includes Active Lists. You can now compile customized lists of important resources such as nets, macros, regions, and instances. Lists are updated dynamically when the design objects' state changes. This feature makes it very easy to track resources and floorplan the design.

ACTgen Core Generator

RAM Enhancements for Axcelerator supports full RAM cascading, including variable aspect data widths. Variable aspect ratios, enabled for 2 port and dual port RAMs, plus depth and width cascading is provided.
New RAM initialization for ProASIC3 and Axcelerator devices. This memory editor provides an intuitive way of specifying the memory content during the design phase instead of the simulation stage, reducing the simulation cycle time. This is especially useful in the case of variable aspect ratio RAMs.

ProASIC3 Specific Enhancements

A new automatic "Local Clock Assignment" (LCA) feature detects if there are more than 6 global nets coming from the user netlist or PDC constraints and if so, automatically assigns the global nets to either chip or quadrant regions.
A high effort Timing-Driven Place-and-Route flow can improve device performance 7% (average) however there will be a significant run time increase. A small percentage performance improvement may take several hours, depending on the device size and complexity.
An enhanced incremental router flow preserves previous routing and allows a true ECO mode when recompiling, importing an ECO netlist, or making minor modifications in global assignments and regions.
Design specific IBIS models can now be exported after place-and-route. The generated IBIS file includes package, package pin numbers, signal names, and I/O models.
New "Global Routing" techniques significantly reduce routing run times, especially in large devices.

ProASIC^PLUS and 500k Routability Enhancements

A new routing algorithm improves the routability of congested designs. Previously un-routable designs may succeed by using a lower Timing Weight selection. Performance may degrade in some cases.

New Package Support

Axcelerator Packages

AX1000 624 LGA
AX2000 624 LGA
AX2000 1152 LGA
RTAX1000S 624 LGA
RTAX2000S 624 LGA
RTAX2000S 1152 LGA

SX-S Packages

SX32A 84 CQFP
RTSX32S 84 CQFP
RTSX72S 624 LGA

ProASIC^PLUS Packages

APA600 624 LGA
APA1000 624 LGA
APA1000 1152 LGA

46690 - New ProASIC3/E I/O specifications. The ProASIC3/E datasheet has been modified with new I/O limitations as follows:

For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in the east and west banks cannot exceed 15. Refer to package pin list in the datasheet for position assignments of the 15 LVPECL pairs. A3P400 will be available in a future software release.

46661 - SmartTime Constraints Editor checks imported SDC file for errors. If any errors are found, SmartTime generates an error. You must manually correct the error and re-import the file into SmartTime. This is a different behavior from previous SDC import where error checking is done later in the flow.

43901 - DCF support for AX devices will be obsolete after v6.2. Designer Constraint Format (DCF), historically used by Timer for timing constraints, will not be supported in subsequent releases. Customers should convert DCF files to SDC. After v6.2, Libero/Designer will not import or export DCF files.

Operating System Final Support

This release is the final support for:

Windows NT (Libero/Designer)
RedHat Linux 8 (Designer)
RedHat Linux 9 (Designer)

Designer v6.2 requires a current Designer v6.0 license.

Designer Gold is FREE development software, supporting Actel devices through 300k gates plus the A3P400 and A3P600E devices.

45 day Free Evaluation Licenses, supporting all devices, are also available but do not support device programming.

Designer Platinum is available for purchase at Actel authorized distributors or sales offices.

Check out the software editions and license charts for descriptions of the tools and available licenses. To register for your FREE license, go to the Software Licenses and Registration System.

Items in this section relate to previously published workarounds for known issues. Workarounds are no longer required for the following issues:

24177 - Designer software locks EDIF source file after compile

31795 - Fanout Display in Timer Does not Match the Display in MVN

31813 - Timing violation report and GUI slack reporting do not match

32033 - The dont_optimize or don't_touch GCF Constraints are not recognized after layout

32132 - HDL check on "when" statements gives warning

32342 - Hold Check Analysis does not support multi-cycle constraints

32346 - Sort-by-slack in not supported for min delay analysis

33574 - Multi-cycle path constraints are not taken into account for clock frequency Calculation

35515 - Error messages when using unsupported constraint

35804 - SmartPower exits unexpectedly if a top level instance shares the same name as the top level

36690 - Resource count provided by prelayout checker is incorrect when regions intersect

37006 - ACTgen generated the wrong netlist for pipelined barrel shifter

37021 - 40950 - ACTgen does not allow a variable aspect ratio for dual port RAM

37815 - Designer state doesn't get reset when new implementation is created

38281 - set_false_path -through constraint is ignored in gcf2sdf for PALACE

39631 - Timer must be restarted to show false path effects on External Setup and Hold Values

39890 - Region snapping is not functioning correctly when crossing boundaries

39994 - Exported SDC on enabled flip-flops do not match the netlist

40052 - Warning message appears when a combined register has a constraint

41266 - Constraints on instances with "\" in the Name are not usable in TDPR for SX-A and older families

PALACE

46941 - The "Keep_Device" command does not necessarily keep the design from being promoted to a larger device if the device utilization is high. During the optimization process, if a device is very full, PALACE attempts to stay within the targeted device using "Keep_Device", however this does not guarantee that promotion to a larger device will not occur.

ACTgen

46305 - PLL External Feedback is not available. In v6.2, EXTFB is grayed out and therefore unavailable in the PLL configuration user interface. EXTFB was available in Libero/Designer v6.1 but is temporarily disabled. This feature will be available in a future release. (A3P/E)

45617 - ACTgen hangs when RAM with Max depth/width is being generated (A3P/E)

46618 - Mentor Graphics DX Designer support in ACTgen is discontinued. ACTgen symbol generation is no longer compatible with recent versions of DX Designer.

44172 - PLL clock alignment based on output divider value (APA)

47409 - Exporting IBIS file will error out if the file name contains upper-case characters. Ensure that the file name does not contain upper-case characters. (ProASIC3/E)

30859 - Post-combiner device utilization is confusing

47296 - Re-compile flow may require re-import (ProASIC3/E)

47246 - Layout detects false combinational loop (SX-A, eX, RTSX-S, ProASIC, ProASIC^PLUS)

47474 - Need to regenerate PLL to have new properties (ProASIC3/E)

Solaris and Linux

46240 - Use of large fonts causes dialog boxes to be too large and constraints cannot be entered (all devices)

47466 - Tool Tips on Linux not showing in User Interface. Tool tips do not always show when pointing to Icons or other elements. This is a known issue and will be resolved in a future release.

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