Designer v6.1 Service Pack 1 (SP1) Release Notes
(Mar 2005)
Thank you for your interest in Actel's Designer FPGA physical implementation
v6.1 Service Pack 1 software. These release notes outline various updates
for the v6.1 SP1 software.
ProASIC3
- Program (STAPL) file generation is enabled for A3PE600 ProASIC3E
- Requires FlashPro3 programmer and FlashPro v3.3 software
- Improved ACTgen PLL generator interface provides more accurate delay
numbers based on ProASIC3 capability
- New packages for ProASIC3
| Device |
Package |
Speed |
Voltage |
Temp Rng |
Silver |
Gold |
Platinum |
| A3P125 |
144 FBGA |
STD, -1, -2 |
1.5 |
Com, Ind |
Y |
Y |
Y |
| A3P125 |
144 FBGA |
-F |
1.5 |
Com |
Y |
Y |
Y |
| A3P1000 |
144 FBGA |
STD, -1, -2 |
1.5 |
Com,Ind |
N |
N |
Y |
| A3P1000 |
144 FBGA |
-F |
1.5 |
Com |
N |
N |
Y |
Other device support additions
or changes:
- Programming yield improvement for AX and RTAXS. This service pack includes
enhancements that may increase the programming yield for AX and RTAXS
devices.
- For RTAXS designs created prior to v6.1 SP1, the software will automatically
detect if the design will benefit from the v6.1 SP1 enhancements when
the .adb file is opened. If yes, the previous routing will be invalidated
and the user will be prompted to re-route the design using v6.1 SP1
- For AX designs created prior to v6.1 SP1, the routing will not be
automatically invalidated, however Actel recommends that the design
be re-routed so it can benefit from potential yield enhancements
- RT54SXS-S and RTSX-SU AFM updates to improve programming yield
- AFMs generated with v6.1 SP1 require Silicon Sculptor v3.87 (DOS)/v4.50.0
(Windows) be used for programming
- RTAX-S and AX
- Prior to Libero IDE and Designer v6.1 Service Pack 1, the Axcelerator
and RTAX-S simulation libraries did not accurately reflect an EMPTY
flag behavior. The libraries did not model an EMPTY flag temporary
low period after the release of CLR during the high RCLK pulse. These
simulation libraries have been corrected in Libero IDE and Designer
v6.1 SP1 to reflect the true silicon behavior of the EMPTY flag. An
apps note covering this issue is available.
- Added MIL temp range for A54SX72A FG256 and FG484 for STD and -1 speed
grades
- Removed -3 speed grade for all Axcelerator (AX) devices
- The user will be informed if an existing .adb uses -3 and proceed
to automatically convert the design to -2
- Removed -3 speed grade for A54SX08A device
- The user will be informed if an existing .adb uses -3 and proceed
to automatically convert the design to -2
- Added RTAX2000S in CG1152 package
| Family |
Die |
Package |
Speeds |
Voltage |
Ranges |
Silver |
Gold |
Platinum |
| Axcelerator |
RTAX2000S |
1152 CCGA |
STD |
1.5 |
MIL |
N |
N |
Y |
| Axcelerator |
RTAX2000S |
1152 CCGA |
-1 |
1.5 |
MIL |
N |
N |
Y |
Requirements for ProASIC and ProASICPLUS Users
If customers have not already done so, all ProASIC and ProASICPLUS designs
must be upgraded to Libero/Designer version 6.1 which was released January
2005. Downloads of this software are available at the
Libero IDE v6.1 Release Notes
or Designer v6.1 Release Notes.
Important place-and-route software changes have been made that must be
factored into your design to ensure proper handling of all conditions.
Windows NT Support
Libero and Designer will no longer be available or supported on Windows
NT after 2005.
GCF Timing Support
GCF Timing Constraint support for ProASICPlus (APA) family is being obsoleted.
Libero and Designer v6.1 SP1 will be the last version supporting GCF to
SDC conversion for the following GCF timing constraints. Subsequent releases
of Libero and Designer will not recognize these constraints. For any APA
design-in-process that is expected to be completed on a future software
release, customers should remove these GCF timing constraints from their
GCF files and substitute them with an equivalent SDC constraint. SDC files
can be imported into Designer or generated by the Timer user interface
(pre-layout).
The GCF constraints to be obsolete after v6.1 SP1 are shown below, along
with the corresponding SDC.
| GCF Constraint |
SDC Constraint |
| create_clock -period <period_value> portname |
create_clock -period period_value portname |
| create_clock -period <period_value> netname |
create_clock -period period_value potential_clock_port_pin_name |
| set_false_path [-from from_port][-through any_port][-to to_port] |
set_false_path -through through_list |
| set_input_to_register_delay <delay> [-from inp_port] |
set_max_delay delay_value [-from from_list][-to to_list] |
| set_multicycle_path <num_cycles> -from reg_port [-through_any_port]
[-to_port] |
set_multicycle_path path_multiplier [-from from_list][-to to_list] |
| set_register_to_output_delay <delay> -to out_port |
set_max_delay delay_value [-from from_list][-to to_list] |
| set_max_delay -from first_pin_in_the_list -to last_pin_in_the_list |
set_max_delay delay_value [-from from_list][-to to_list] |
Designer v6.1 SP1 requires a current Designer v6.0 license.
