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Designer v6.1 Release Notes

(updated Apr 1, 2005)

Thank you for your interest in Actel's Designer v6.1 FPGA physical design implementation software. These release notes outline various updates for the v6.1 software.

What's New in this Release

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ProASIC3 Support Now supporting ProASIC3/E

This release introduces initial support for Actel's new low cost ProASIC3 (A3P) and ProASIC3E Flash (A3PE) Family devices. Designer v6.1 provides full design flow support including:

  • ACTgen core support for ProASIC3 features:
    • Clock Conditioning Capability (CCC) and PLL definitions via a Visual PLL Core Generator Wizard
    • Dual-Port RAM and FIFO configurations
    • 1kbit user Flash ROM (FROM)
  • FROM Simulation Flow
  • Import and use of PDC (Physical Design Constraints) and SDC (Synopsys Design Constraints)
  • Multiple Compile options:
    • combine registers with I/Os
    • superior global spines management
    • automatic global promotion
    • local clock maximum shared instances
    • local clock buffer fan out selection
  • Enhanced Compile Reporting
  • MultiView Navigator enhancements
    • I/O Attribute Editor supports the wide range of I/O choices in ProASIC3
    • Create Quadrant and Local Clock regions with ChipPlanner
  • Efficient timing-driven place-and-route process
  • Timer support for SDC constraints and pre/post-timing analysis
  • New back-annotation timing flow
  • Post layout power analysis

Note: Designer v6.1 does not support program file generation or device programming for ProASIC3 or ProASIC3E.

ProASIC3 devices and packages supported in Designer v6.1

Device Package Speed Voltage Temp Rng Gold Platinum
A3P060 100 VQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P060 100 VQFP -F 1.5 Com Y Y
A3P060 144 FBGA STD, -1, -2 1.5 Com, Ind Y Y
A3P060 144 FBGA -F 1.5 Com Y Y
A3P060 144 TQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P060 144 TQFP -F 1.5 Com Y Y
A3P125 100 VQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P125 100 VQFP -F 1.5 Com Y Y
A3P125 144 TQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P125 144 TQFP -F 1.5 Com Y Y
A3P125 208 PQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P125 208 PQFP -F 1.5 Com Y Y
A3P250 100 VQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P250 100 VQFP -F 1.5 Com Y Y
A3P250 144 FBGA STD, -1, -2 1.5 Com, Ind Y Y
A3P250 144 FBGA -F 1.5 Com Y Y
A3P250 208 PQFP STD, -1, -2 1.5 Com, Ind Y Y
A3P250 208 PQFP -F 1.5 Com Y Y
A3P250 256 FBGA STD, -1, -2 1.5 Com, Ind Y Y
A3P250 256 FBGA -F 1.5 Com Y Y
A3P400 208 PQFP STD, -1, -2 1.5 Com, Ind N Y
A3P400 208 PQFP -F 1.5 Com N Y
A3P400 256 FBGA STD, -1, -2 1.5 Com, Ind N Y
A3P400 256 FBGA -F 1.5 Com N Y
A3P400 484 FBGA STD, -1, -2 1.5 Com, Ind N Y
A3P400 484 FBGA -F 1.5 Com N Y
A3P600 208 PQFP STD, -1, -2 1.5 Com, Ind N Y
A3P600 208 PQFP -F 1.5 Com N Y
A3P600 256 FBGA STD, -1, -2 1.5 Com, Ind N Y
A3P600 256 FBGA -F 1.5 Com N Y
A3P600 484 FBGA STD, -1, -2 1.5 Com, Ind N Y
A3P600 484 FBGA -F 1.5 Com N Y
A3P1000 208 PQFP STD, -1, -2 1.5 Com, Ind N Y
A3P1000 208 PQFP -F 1.5 Com N Y
A3P1000 256 FBGA STD, -1, -2 1.5 Com, Ind N Y
A3P1000 256 FBGA -F 1.5 Com N Y
A3P1000 484 FBGA STD, -1, -2 1.5 Com, Ind N Y
A3P1000 484 FBGA -F 1.5 Com N Y

ProASIC3E devices and packages supported in Designer v6.1

Device Package Speed Voltage Temp Rng Gold Platinum
A3PE600 208 PQFP STD, -1, -2 1.5 Com, Ind Y Y
A3PE600 208 PQFP -F 1.5 Com Y Y
A3PE600 256 FBGA STD, -1, -2 1.5 Com, Ind Y Y
A3PE600 256 FBGA -F 1.5 Com Y Y
A3PE600 484 FBGA STD, -1, -2 1.5 Com, Ind Y Y
A3PE600 484 FBGA -F 1.5 Com Y Y
A3PE1500 208 PQFP STD, -1, -2 1.5 Com, Ind N Y
A3PE1500 208 PQFP -F 1.5 Com N Y
A3PE3000 208 PQFP STD, -1, -2 1.5 Com, Ind N Y
A3PE3000 208 PQFP -F 1.5 Com N Y

Supporting information for ProASIC3

  • Libero IDE v6.1 Quickstart Guide
  • Application Notes
    • ProASIC3 FlashROM (FROM)
    • ProASIC3 SRAM/FIFO Blocks
    • Using DDR for ProASIC3 Devices
    • Using ProASIC3 Clock Conditioning Circuitry
    • Using Global Resources in ProASIC3
    • ProASIC3 RAM/FIFO Design
    • Using ProASIC3 Security Options
    • Implementing Multipliers in PA3 using RAM
    • ISP for PA3 using FlashPro3
Included Software
  • FlashPro 3.2 (Same as Libero IDE v6.0)
  • Silicon Explorer v5.0 SP2 (Same as Libero IDE v6.0)
  • ChainBuilder v1.0 (Same as Libero IDE v6.0)
Optional Software
  • PALACE 2.0 Physical Synthesis
    PALACE 2.0 introduces full support for Actel's new ProASIC3 and ProASIC3E families, in addition to ProASICPLUS. Adding PALACE v2.0 into the design flow will deliver a performance improvement of one additional speed grade for most designs.
    Note: PALACE 2.0 on Solaris OS is not available at this time.
  • Synplify Pro AE 7.7.1 Synthesis
    Synplify Pro AE 7.7.1b introduces full synthesis support for the new ProASIC3 family devices.
  • Mentor Graphics Synthesis support for PROASIC3
    Synthesis support for ProASIC3 is provided by Mentor Graphics as follows:

Important Notices

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Requirements for ProASIC and ProASICPLUS Users

All ProASIC and ProASICPLUS customers are required to upgrade their existing designs to Libero/Designer version 6.1. Important place-and-route software changes have been made that must be factored into your design to ensure proper handling of all conditions.

Red Hat Linux & Windows NT Support

Designer v6.1 is supported on RedHat RH Enterprise Linux 3.0.
2005 is the last year Designer will be supported on Windows NT

GCF Timing Support

GCF Timing Constraint support for ProASICPLUS (APA) family is being obsoleted. Libero and Designer v6.1 (and service packs) will be the last version supporting GCF to SDC conversion of the following GCF timing constraints for APA devices. Subsequent releases of Libero and Designer will not recognize these constraints. For any APA design-in-process that is expected to be run on releases following v6.1, customers should take care now to remove these GCF timing constraints from their GCF files and substitute them with an equivalent SDC constraint file (exported automatically by Designer after a GCF import or manually through Designer interface).

The GCF constraints being obsoleted are shown below, along with the corresponding SDC.

GCF Constraint SDC Constraint
create_clock -period <period_value> portname create_clock -period period_value portname
create_clock -period <period_value> netname create_clock -period period_value potential_clock_port_pin_name
set_false_path [-from from_port][-through any_port][-to to_port] set_false_path -through through_list
set_input_to_register_delay <delay> [-from inp_port] set_max_delay delay_value [-from from_list][-to to_list]
set_multicycle_path <num_cycles> -from reg_port [-through_any_port] [-to_port] set_multicycle_path path_multiplier [-from from_list][-to to_list]
set_register_to_output_delay <delay> -to out_port set_max_delay delay_value [-from from_list][-to to_list]
set_max_delay -from first_pin_in_the_list -to last_pin_in_the_list set_max_delay delay_value [-from from_list][-to to_list]

Licensing

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Designer v6.1 requires a current Libero IDE v6.0 license. No license upgrade is required.

Resolved Issues

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Items in this section relate to previously published workarounds for known issues. Workarounds are no longer required for the following issues:

28446 - Using GLPEMIB macro in ProASICPLUS

28588 - Timer does not show delay from input pad to PLLs

30557 - ProASICPLUS Async-RAM Simulation Does Not Allow Read/Write At Same Location At The Same Time

31982 - PDC treats illegal Local clock resource type as region name

32716 - Timer shows zero cell delay for OUTBUF

32806 - Moving from Ratsnest to Routing View Not Displayed On First Attempt

32917 - Placement Fails Even for Utilization of Defined Region Less than 50%

33978 - Layout Fails When Assigning < net >_ BUF_AUTO Macros to a User-Defined Region

36528 - Refresh Problem When Unassigning Differential I/Os in PinEditor

37071 - If LocalClock Region Cannot be Created Due to Insufficient Resource, Macros are Left Unplaced

37225 - "Assertion Failed" Error in Console Window When Exiting MVN on UNIX Platform

37228 - "Assertion Failed" Error Occurs When Moving or Resizing Exclusive Region with Fixed Logic in the Region

37233 - Exported PDC with Exclusive Regions Cannot Be Imported and Re-Compiled by Designer

37386 - Layout is invalidated if MVN is open and user clicks on Layout

38309 - Can't import .GEN files in Libero

40672 - INOUT bus with initial value 'U' Within Netlist Causes Unknown In Post-Synthesis and Post-Layout Simulation

41310 - APA vital library cannot simulate certain PLL clkout delay

New Known Limitations, Issues and Workarounds

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39843/39844 - Previously created ProASIC3 or ProASIC3E ADB files are not usable. Any previously created ProASIC3/E design using pre-production software is not compatible with v6.1 and must be re-created using v6.1. Do not use an ADB file generated by pre-v6.1 production software (EAP, Test, FAE).

STAPL (Programming) file generation is NOT supported in Libero/Designer v6.1 for ProASIC3 or ProASIC3E. All other families are supported.

39863 - Minibanks for ProASIC3 or ProASIC3E are not supported. Minbanks, as referenced in the ProASIC3 or ProASIC3E datasheet, are not supported in v6.1

39816/42903 - ProASIC3 I/O GTLP software values exceed datasheet values. In v6.1 software:

  • gtlp25_vol_5x datasheet value is 33mA and the software limit is 40 mA
  • gtlp33_vol_5x datasheet value is 35mA and the software limit is 51 mA
Both meet the GTLP industry specification of minimum 24mA.

FlashPro: Only FlashPro 3.2 (or earlier) can be used with Libero/Designer v6.1

ACTgen

37006 - 43541 - ACTgen generates wrong netlist for pipelined barrel shifter (ProASIC3, ProASIC3E, and AX devices)

35109 - When EDAC macros are imported from one workspace to another, the EDAC IP macros edaci_* are not copied into the workspace. The user must regenerate the EDAC macro to be included in the workspace. (AX family)

37021 - 40950 - 43546 - ACTgen does not allow variable aspect ratios for dual port RAM (ProASIC3, ProASIC3E, and AX devices)

41196 - 37242 RAM blockage usage issue (ProASIC3 and ProASIC3E devices)

41198 - 37072 FIFO controller issue (ProASIC3 and ProASIC3E devices)

Designer

25695 - Power values are not dynamically updated when output load changed (ProASICPLUS and ProASIC3E devices)

34331 - Placement fails due to IO + Region constraints not snapping (ProASICPLUS and ProASIC3E devices)

38402 - Clock placer puts clocks in regions with insufficient I/O resources (ProASIC3E and AX devices)

42854 - Designer crashes when compile option - demote global nets is turned on (ProASIC3 and ProASIC3E devices)

43069 - Designer crashes when compile option - demote global nets is turned on for very low fanout nets (ProASICPLUS and ProASIC3E devices)

Multiview Navigator

36690 - Resource Count provided by Prelayout checker is incorrect when Regions intersect

39890 - Region snapping is not functioning correctly when crossing boundaries

Timer

39994 - Exported SDC Constraints on Enabled Flip-Flops Do Not Match the Netlist (ProASICPLUS and ProASIC3E devices)

40052 - Warning Message Appears When a Combined Register Has a Constraint (ProASICPLUS and ProASIC3E devices)

41266 - TDPR cannot use constraint set (SXA devices)

42752 - Missing path in timing report from input to WRB ram pin (ProASIC3, APA, AX, SXA devices)

PALACE

41448 - PALACE must have physical effort set to effort 1 on designs that have multi-technology I/Os (ProASIC3E devices)

Previous Known Issues and Workarounds

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Designer v6.0 SP3 Release Notes

Designer v6.0 SP2 Release Notes

Designer v6.0 SP1 Release Notes

Designer v6.0 Release Notes

Designer v5.2 SP1 Release Notes

Designer v5.2 Release Notes

Designer 5.1 Release Notes

Designer 5.0 SP1 Release Notes

Designer 5.0 Release Notes

Download and Install Designer v6.1

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The version of software that you requested is no longer the most current version available. Please download the most recent software update.

If you need this specific version of software, please contact Actel Tech Support:
Email: tech@actel.com
Phone: 1.800.262.1060