Designer v6.0 SP3 Release Notes
Thank you for your interest in Actel's Designer v6.0 SP3 physical implementation
software. These release notes outline various updates for the v6.0 software.
This Service Pack delivers software enhancements that may increase programming
yield for AX and RTAXS devices.
Designs created prior to v6.0 SP3
For RTAXS designs created using previous releases, the software will
automatically detect if the design will benefit from the v6.0 SP3 enhancements
when the .adb file is opened. If yes, routing will be invalidated and
the user will be prompted to re-route the design using v6.0 SP3.
For AX, routing will not be invalidated, however, Actel recommends
that the design be re-routed using v6.0 SP3 so that it can take advantage
of the yield enhancements.
Other Significant Fixes:
41890 - In Libero/Designer v6.0 SP2, the SDF and the
VITAL simulation libraries exhibit mismatch in timing arc definition
for some specific applications of RAM/FIFO in AX family devices. SP3
removes these inconsistencies between Verilog and VITAL libraries, and
the SDF.
Designer v6.0 SP3 requires a current Designer v6.0 license.
Items in this section relate to previously published workarounds
for known issues. Workarounds are no longer required for the following
issues:
None.
