Designer v6.0 Release Notes
Thank you for your interest in Actel's Designer v6.0 physical implementation
software. These release notes outline new features and benefits, new
device support, known limitations, and other detailed information about
this release.
New Device Support
- AX1000 in CG624 package
- AX250 in CQ208 and CQ352 packages
- RTAX250S in CQ352 and CQ208 packages
ACTgen
Selecting and configuring an ACTgen core is significantly easier through
a redesigned user interface. New functions include:
- Find a specific core by scanning and selecting from
- an alphabetized list of categories (arithmetic, comparators,
counters,)
- an alphabetized list of all macro functions for your device
- View
- only cores associated with a family
- all cores within a category
- all cores in a functional type
- the version of a core
- brief description of any core
- a "Configured Core View" workspace that shows all cores
selected and configured for the project
MultiView Navigator
The MVN supports new features enhancing overall usability.
Logical Cones - Logical cones enable you to view, highlight,
and cross-probe a selected subset of your netlist. Use this when iterating
timing closure for better visibility into your design.
Active Message System (AMS) - AMS gives you immediate
feedback on the last action performed in hierarchical order.
Prelayout Checker - An improved Prelayout Checker detects
constraint errors earlier in the design flow.
Include RAM and I/O in Spine and Net Regions Feature (ProASIC,
ProASICPLUS Families) - This option affects
the behavior of 1) the use_global constraint, 2) the set_net_region
constraint, and 3) the creation of spines in the MultiView Navigator.
- Selecting "Include RAM and I/O in Spine and Net Regions"
from the Compile Option enables you to assign memory and I/O to spine
(LocalClock) and net regions. When this option is checked, Designer
will apply the use_global and set_net_region constraints to core
cells, memory, and I/O. When unchecked, Designer applies the use_global
and set_net_region constraints to core cells only. For new designs,
this box is automatically checked. f a design created using Libero
or Designer v5.2 SP1 or earlier is opened with v6.0, this Compile
Option is unchecked by default. If you change this default setting,
you must recompile your design.
- This option also determines whether memory and I/O are included
in a LocalClock region that you create with the ChipPlanner tool. If
checked, memory and I/O are included. If not checked, they are excluded.
Other MVN Ease of Use Improvements
- Each logical instance in the Hierarchy Window and the Find Results
tabs have a Properties option from which you can copy an instance name
and location.
- The Properties dialog box now shows the Location, Region Constraint,
Cell Name, and Netlist properties of the logical instance.
- Drivers of nets are now shown in the Nets tab in the Hierarchy Window
of the MVN.
- You may control the color of individual regions for enhanced visibility.
Timer / Timing Engine
The Timer tool has the following new features:
- Importing SDC (Synopsys Design Constraints) as a source file
- Both the netlist and timing constraints (SDC File) can be imported
at the same time in a pre-compiled state
- Designer audits the SDC file and can detect any changes or updates
made to the original file. This feature helps in passing SDC files
created by third party tools.
- Improved constraints flow for ProASICPLUS family
devices through improved pin name mapping; SDC constraints entered
in the Timer user interface (using SDC import or generated within Designer)
are mapped to original netlist names, saved correctly in the database,
and correctly exported to third-party tools.
- Timer
- Clock frequency estimation accounts for Duty Cycle. The value
specified in the clock constraint for the duty cycle is now taken
into account in the clock frequency. When the user enters a clock
constraint in the Timer GUI, the frequency estimated by Timer is
discarded, and the max frequency now appears in the summary tab
with the duty cycle taken into account.
ProASICPLUS Performance
ProASICPLUS family device performance has been improved
10% on average via improvements in Timing Driven Place
& Route (TDPR), improved routing algorithms, and congestion relief.
Up to 40% improvement has been seen in some complex designs, and previously
un-routable designs are now routing with v6.0.
New Operating System Support
- RedHat Linux 8
- RedHat Linux 9
- Solaris 9
Note 1: This is the last Designer version supported on Solaris 7 and
Red Hat Linux 7.1 platforms.
Note 2: See Known Issues and comments regarding Linux and Solaris systems
in the Known Issues Section below.
For existing users, Designer v6.0 requires a license upgrade. Customers
with current paid licenses will automatically receive an updated license.
Please carefully follow the instructions in the update license email
to install your license properly.
FlexLM license manager is upgraded by Actel to version 10.0. Designer
floating license servers must be upgraded to a version 10.0 daemon (lmgrd).
Designer v6.0 contains the following:
- Actel ChainBuilder v1.0
- Actel FlashPro v3.2
- Actel Silicon Explorer II v5.0 SP2
- Actel Designer v6.0, capture 6.0.0.133
