Designer v5.2 Release Notes
Thank you for your interest in Actel's Designer v5.2. These v5.2 release
notes outline new features and benefits, new device support, known limitations,
and other information about this release.
Actel Designer v5.2
Actel Chainbuilder v1.0
Linux Red Hat 7.1 for Designer
Version 5.2 supports Actel Designer on Linux Red Hat 7.1. Functionality
is basically the same as Solaris, except where noted in the Linux section
in these release notes. Also see System
Requirements for Linux systems.
ChainBuilder
The ChainBuilder tool enables you to use ISP (In System Programming)
via a single JTAG header to program a chain of several devices. The chain
may contain programmable and non-programmable devices such as FPGAs,
microprocessors, logic, microcontrollers, or other types of ICs. The
tool creates a concatenated STAPL file from individual STAPL files for
programming the targeted Actel Flash FPGA devices. ChainBuilder automatically
detects of all the devices in the chain, and you can select the devices
to program. Each of the devices in the chain is programmed sequentially.
Visit the ChainBuilder
web page to learn more.
ProASICPLUS: Next Generation Timer –
Timing Driven Place-and-Route (NGT-TDPR)
A new timing driven place-and-route flow implements closer coupling
of the Timer with Layout and may eliminate the need for additional physical
constraints. You can enter timing constraints through the Timer GUI or
by importing SDC files. Existing GCF files are converted by an internal
GCF-to-SDC conversion process. See the app note ProASICPLUS Timing Driven
Flow in Libero/Designer 5.2.
ProASICPLUS: ChipPlanner/MultiView Navigator
(MVN): Set Memory Region
A new Set_Memory_Region constraint has been added to enable you to set
memory regions and constrain memory placement. This option can either
be used in GCF flow or via the MultiView Navigator GUI.
ProASICPLUS: ChipPlanner/MultiView Navigator
(MVN): Create & Edit Spines
You can now create and edit spines in the MVN GUI.
Incremental routing for Axcelerator
The Axcelerator Layout Options GUI now provides an incremental-route
option for AX Routing. When invoking Layout for Axcelerator, the Layout
Options dialog now contains an additional checkbox for Route.
Clock Segmentation support for Axcelerator
Currently you can assign nets to clock resources at the chip level.
V5.2 gives you more control over the local clock resource you use on
a Tile level. This makes local clocks that belong to other Tiles’
available for use independently. This release requires that you specify
these clock constraints in a batch mode using the PDC file. A graphical
constraint creation/manipulation will be addressed at a later time.
Timer Improvements
By default, Timer now sorts the paths displayed in the Paths tab by "Slack".
The Summary tab in Timer now includes the graphic display of the clock
edge information for the critical path.
SmartPower
Device specific static power reporting included in this release.
ProASICPLUS devices now available in Automotive
Temp Ranges
Temperature Range: -40 C to +125 C Junction Temperature
Voltage:
| Base Voltage |
Minimum |
Typcal |
Maximum |
| 2.5 |
2.37 |
2.5 |
2.62 |
| |
TQ100A |
PQ208A |
FG144 |
FG256A |
FG484 |
FG896 |
| APA075 |
X |
X |
X |
|
|
|
| APA150 |
X |
X |
X |
X |
|
|
| APA300 |
|
X |
X |
X |
|
|
| APA450 |
|
X |
X |
X |
X |
|
| APA600 |
|
X |
|
X |
X |
|
| APA750 |
|
X |
|
|
|
X |
| APA1000 |
|
X |
|
|
|
X |
