Actel

Designer v5.1 Release Notes

Thank you for your interest in Actel's Designer v5.1 . These v5.1 release notes outline new features and benefits, new device support, known limitations, and other information about this release.

Included Software

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Designer v5.1

New Features and Enhancements

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Designer Gold now supports newer Actel devices up to and including 300k gates.

New Packages for ProASICPLUS. The following Military Temperature range packages are now available:

Device Packages Speed Grade
APA300 352 CQFP STD
APA300 208 CQFP STD
APA600 352 CQFP STD
APA600 208 CQFP STD
APA100 208 CQFP STD

New Packages for Axcelerator. The following Military Temperature range packages are now available:

Device Packages Speed Grade
AX500 352 CQFP STD, -1
AX500 208 CQFP STD, -1
AX1000 352 CQFP STD, -1

RTSX-S -2 speed grade discontinued. The -2 speed grade for the RTSX-S device family has been discontinued starting in v5.1.

Resolved Issues

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AX2000/RTAX2000S designs generated on v5.0 SP1 or earlier must go through re-layout in Libero/Designer v5.1 before generating an AFM file. If you want to keep the existing placement, run layout with incremental fix placement.

26434 - In ProASIC and ProASICPLUS families, FIFO Flags do not behave properly for the LEVEL signal. The LEVEL signal interpretation is wrong in R1-2003. In simulation models, the value is one more than it should be. This issue is resolved in Libero/Designer v5.0.

32047 – For AX designs only, the SDF back-annotated timing for the BIBUF macro did not take into account the net delay on the data to PAD path.

32842 – Using Windows/Chinese environment, Timer would crash using the Paths function. This problem is resolved in v5.1.

New Known Issues and Workarounds

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Click any of the listed issues for a description and workaround.

APA/ProASICPLUS

33063 - Issue with pin TCL command support for APA

32499 - Synplify Duplicates DMUX components to satisfy fan-out limit limitation in the length of the GCF Constraint File(s) name

32266 - set_io GCF Constraint is ignored in Designer 5.0

35198 - Limitation in the length of the GCF constraint file names

Designer Known Issues

Timer

28588 - Timer does not show delay from input pad to PLLs

31813 - Timing violation report and GUI slack reporting do not match

31977 - Timer must take into account Duty Cycle during Frequency computation

32716 - Timer shows zero cell delay for OUTBUF

32047 – For AX designs only, the SDF back-annotated timing for the BIBUF macro does not take into account the net delay on the data to PAD path.

ACTgen

31444 – Deeply cascaded FIFOs generated in ACTgen may be generated incorrectly

Designer Miscellaneous

31694 - PLL does not lock in post-layout simulation

33094 - Probe file contains net names that get modified by Designer

33065 - Thread panic error message or Designer hangs during a major design flow operation (MVN, Compile, Layout)

Designer MultiView Navigator

33113 - Chip planner shows output net of GLINT is connected as _Regular_

32917 - Placement fails with utilization of the defined region less than 50%

32009 - Top level view is displayed in Netlist Viewer when cross-probing from Timer

31982 - PDC treats illegal local clock resource type as a region name

31430 - Connecting nets are not shown in the Netlist Viewer

31324 - Selecting regions with the Regions tab does not select the region in ChipPlanner

31317 - Tooltip shows 8 PLLs needed but there are only 4 PLLs in the design

30847 - When moving a region, a WARNING message is not relevant and content is wrong

30846 - When moving a region, an ERROR message is not relevant and content is wrong

28930 - MVN crashes when attempting to print from ChipEditor, PinEditor, and NetListViewer

33603 – I/O Attribute Editor does not show updated I/O standard if default I/O standard is changed in Device Selection

Fuse - Axcelerator

30653 – Attempting to generate a fuse file after assigning an additional VREF pin to a placed-and-routed design without re-running layout can cause Designer to exit prematurely. Run layout with incremental fixed “on” before running the “Fuse” command.

Scripting

33272- Braket and dollar signs must be ESCAPED when you use them in PDC/Tcl

Download and Install Designer v5.1

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The version of software that you requested is no longer the most current version available. Please download the most recent software update.

If you need this specific version of software, please contact Actel Tech Support:
Email: tech@actel.com
Phone: 1.800.262.1060