Designer 5.0 with Service Pack 1 for HP-UX
Designer Version 5.0.1.9
If you are designing with large ProASICPLUS devices,
please review issue number 32744 before
installing Designer 5.0 with Service Pack 1 for the HP-UX 11.0 platform.
Please click here to
view device specific memory requirements.
HP-UX
HP-UX users must ensure that the following HP-UX operating system patches
are installed:
- Wind-U patches which includes the following:
PHCO_23651, "fsck_vxfs(1M) cumulative patch"
PHCO_27375, "cumulative SAM/ObAM patch"
PHCO_26017, "user/group(add/mod/del) cumulative patch"
PHCO_28425, "libc cumulative patch"
PHCO_26111, "libc cumulative header file patch"
PHCO_28630, "bdf(1M) cumulative patch; large file support"
PHKL_28766, "Probe,IDDS,PM,VM,PA-8700,AIO,T600,FS,PDC,CLK"
PHKL_18543, "PM/VM/UFS/async/scsi/io/DMAPI/JFS/perf patch"
PHKL_28593, "VxFS 3.1 cumulative patch: CR_EIEM"
PHKL_20016, "2nd CPU not recognized in G70/H70/I70"
PHKL_27813, "POSIX AIO;getdirentries;MVFS;rcp;mmap/IDS"
PHKL_22589, "POSIX AIO;getdirentries;MVFS;rcp;mmap/IDS"
PHNE_28567, "ONC/NFS General Release/Performance Patch"
PHKL_23409, "NFS, Large Data Space, kernel memory leak"
PHKL_22840, "IDS/9000; file/socket syscalls; eventports"
PHNE_28538, "cumulative ARPA Transport patch"
PHNE_27902, "Cumulative STREAMS Patch"
PHSS_28434, "ld(1) and linker tools cumulative patch"
PHSS_20975, "HP aC++ (A.03.15)"PHSS_26945, "
HP aC++ -AA runtime libraries (aCC A.03.37)"
- "libpthread" patch:
PHCO_29108, "Pthread library cumulative patch"
- X/Motif patches:
PHSS_28874, "X/Motif 32bit Runtime patch"
PHSS_28367, "X/Motif 32bit DevKit Periodic"
HP-UX
Designer 5.0 with SP1 will be the last version
of Designer software that supports the HP-UX operating system. Actel
will maintain support for users of this operating system for one year,
but Actel recommends that you migrate to a supported operating system
as soon as possible.
Axcelerator
PerPin FIFO support is no longer available in Axcelerator devices. Designs
that previously utilized the PerPin FIFO should be modified to remove
them.
Military temperature plastic packages for Axcelerator
The Axcelerator devices are now supported in the following military
temperature rated plastic packages. Timing values have been updated to
support these devices in the military operating conditions.
| Device |
Packages |
Speed Grade |
| AX250 |
208 PQFP |
STD, -1 |
| AX250 |
256 FBGA |
STD, -1 |
| AX250 |
484 FBGA |
STD, -1 |
| AX500 |
208 PQFP |
STD, -1 |
| AX500 |
484 FBGA |
STD, -1 |
| AX500 |
676 FPGA |
STD, -1 |
| AX1000 |
484 FPGA |
STD, -1 |
| AX1000 |
676 FBGA |
STD, -1 |
| AX1000 |
729 BGA |
STD, -1 |
| AX1000 |
896 FGBA |
STD, -1 |
| AX2000 |
896 FBGA |
STD, -1 |
| AX2000 |
1152 FBGA |
STD, -1 |
Military temperature ceramic packages for Axcelerator
The Axcelerator devices are also supported in the following military
temperature rated ceramic packages with timing for the military operating
condition.
| Device |
Packages |
Speed Grade |
| AX2000 |
352 CQFP |
STD |
| AX2000 |
624 CQFP |
STD |
Radiation Tolerant RTAX1000S and RTAX2000S
The RTAX1000S radiation tolerant Axcelerator device for space is now
supported in the following packages and speed grades. This version of
software includes estimated timing values for this device for both pre-radiation
exposure and post radiation exposure. SmartPower does not support power
analysis on radiation exposure and only uses estimated pre-exposure power
values only.
| Device |
Packages |
Speed Grade |
| RTAX1000S |
352 CQFP |
STD, -1 |
| RTAX1000S |
624 CCGA |
STD, -1 |
ProASICPLUS
Military temperature plastic packages for ProASICPLUS
The following ProASICPLUS devices are now available
in the specified mil temp plastic packages.
| Device |
Packages |
Speed Grade |
| APA300 |
208 PQFP |
STD |
| APA300 |
456 BGA |
STD |
| APA600 |
208 PQFP |
STD |
| APA600 |
456 BGA |
STD |
| APA1000 |
208 PQFP |
STD |
| APA1000 |
456 BGA |
STD |
Military temperature ceramic packages for ProASICPLUS
The APA1000 ProASICPLUS device is now supported in
the following military temperature rated ceramic package with timing
for the military operating conditions.
| Device |
Packages |
Speed Grade |
| APA1000 |
352 PQFP |
STD |
Please refer to the ProASICPLUS military grade datasheet
for further details.
Please see the Online Help for
more information on each feature.
ProASIC/ProASICPLUS
Customers using ProASIC or ProASICPLUS devices should
refer to the following application note for additional information on
using Designer 5.0 with their existing designs:
ProASIC and ProASICPLUS Design-Flow Migration to Designer
v5.0
MultiView Navigator
The MultiView Navigator is Actel’s new interface for physical
design constraints and viewing. This interface includes the ChipPlanner
floorplanning tool, PinEditor, I/O attribute editor and Netlist Viewer.
The MultiView Navigator allows for improved crossprobing between these
tools and introduesnew “undo/redo” and find capabilities.
Note that the MVN interface is supported by the ProASIC, ProASICPLUS,
and Axcelerator device families.
ChipPlanner
ChipPlanner is Actel’s new graphical floorplanning tool for the
ProASIC, ProASICPLUS, and Axcelerator families.
For ProASICPLUS customers with existing constraints,
please refer to the following application note: Keeping
Existing Constraints when Using the ChipPlanner with ProASICPLUS
Reports
20503 - “File” > “Find”, and “File” > “Find
Next” have been added to the reports interface.
Timer
For users of the ProASIC and ProASICPLUS devices,
a new tech brief is available that discusses using Timer with the ProASIC
and ProASICPLUS devices.
The following issues have been resolved.
Device Selection Wizard
26972 - Changing the default I/O standard in an existing SX-A design
will no longer invalidate layout.
Layout - Axcelerator
31657 – Layout with effort level set greater then 3 may fail is
region constraints contain a RAM macro. In order to run layout with a
region that contains a RAM macro, start by running layout with effort
less than 4, lock the RAM placement, and re-run layout with effort greater
than 3. This issue has been resolved.
28540 – Designer will accepts designs with a BIBUF macro connected
to the DDR_FIFO macros.
PinEditor
32022/32266 - Issues with set_io constraints and promotion of high fanout
nets to globals have been resolved.
27399 - PinEdit now shows the I/O tile coordinates for ProASICPLUS devices.
ACTgen
23114 - The valid width range for a standard barrel shifter is 2 to
63, and the valid width range for a shift register and a pipe-lined barrel
shifter is 2 to 99. The ACTgen Macros Reference Guide has been updated
with the correct information.
22774 - When generating a PLL for ProASICPLUS in ACTgen,
a secondary frequency was displayed when defaults are chosen even though
there is no real secondary frequency. This issue has been resolved.
26110 – ACTgen now recognizes spaces in the project name and project
path.
Import
24264 - If a file is referenced for import in the GCF using a “/” character,
compile is now recognizes the “/” character and can read
the file.
Timer
29668 - A discrepancy in the slack reported inhe expanded paths and
list of paths have been resolved.
29654 - An issue with adding stop points using wildcards have been
resolved.
29117 - An issue with an anomalous delay reading reported when the
data pin of a CM8 module is connected to the clock network has been resolved.
29114 - An issue with adding new paths to the path set to Timer has
been resolved.
28309 - An issue with calculating clock skew on the Axcelerator family
has been resolved.
29260 - An issue with ordering the display by slack has been resolved.
30052 - An issue with Timer requiring “calculate delays” to
be selected in order to display violations has been resolved.
29630 - An issue with Timer printing text to the unix console while
generating a report has been resolved.
28575 - An issue with the default register to register path through
asynchronous RAM has been resolved.
28673 - An issue with Timer slack calculation has been resolved.
Libraries
26434 – An issue with the level signals on ProASICPLUS FIFOs
asserting one value late has been resolved.
23906 - Vital libraries no longer require that the entity be compiled
before the architecture.
Click any of the links below for a description and workaround.
ACTgen - ProASICPLUS
31444 – Deeply cascaded FIFOs generated in ACTgen may be generated
incorrectly.
Back-Annotation - Axcelerator
32047 – The SDF back-annotated timing for the BIBUF macro does
not take into account the net delay on the data to PAD path.
BSDL Generation - SX-A/SX-S
31327 – Attempting
to generate a design specific BSDL file for the following device/package
combinations may cause Designer to exit prematurely.
| Device |
Package |
| A54SX72A |
624 CCGA |
| A54SX72A |
484 FBGA |
| A54SX72A |
256 CQFP |
| RT54SX32S |
256 CCLG |
| RT54SX32S |
256 CQFP |
| RT54SX32S |
624 CCGA |
| RT54SX72S |
256 CQFP |
ChipPlanner - ProASICPLUS
28117 - Changing the name of a region will not take affect until after
the you press the “OK” button.
27347 - ChipPlanner may not properly warn you if the same macro is assigned
to two separate regions. However, layout detects this error and fails.
29980 - ChipPlanner may show the status of some routed nets as unrouted
in the Axcelerator device even after layout has succeeded. The nets are
routed and the status message is in error. If layout succeeds, the device
has been routed.
29548 - When viewing fan-in nets leading to RAM elements in the ChipPlanner,
some nets may not be drawn all the way to the memory and seem to terminate
before touching the RAM. This is a display issue and the nets are actually
connected to the memory block..
ProASICPLUS
31447 – Repeatedly importing a GCF file that contains a region
constraint creates multiple redundant regions in ChipPlanner.
30538 – Running Designer repeatedly with region constraints may
cause Designer to create multiple redundant regions in ChipPlanner.
Fuse - Axcelerator
30653 – Attempting
to generate a fuse file after assigning an additional VREF pin to a
placed-and-routed design without re-running layout can cause Designer
to exit prematurely. Run layout with incremental fixed “on” before
running the “Fuse” command.
SmartPower
28172 - The clock frequency must be set before the data toggle rate.
Failing to do so causes SmartPower to display inaccurate data toggle
rate.
30096 - Some UNIX users may see the message "Invalid imagelist
handle passed to API" displayed in the console window when starting
SmartPower. You can ignore this message.
Timer
29274 – Timer does not take clock exceptions into account when
computing slack in the expanded path window.
29267 – Timer GUI display does not update when a script is run.
Actel does not recommend running Timer scripts when the Timer GUI is
active.
Layout - ProASICPLUS
32744 - In order to support new features in the software, this version
of Designer may require more memory than previous versions. For certain
large ProASICPLUS designs, functions performed after layout, such as
exporting SDF files, may cause Designer to run out of memory and to exit
with the following error:
ERROR: Assertion Failed in "/vobs/afi/lib/base/src/vfil/vfil1.c",
line 134.
Actel recommends that ProASICPLUS users save the design right
after layout before performing any other functions in order to ensure
that your layout is preserved. Exiting and closing down Designer will
release the used memory. Reopen your design and continue with your post-layout
operation.
Import
29765 – The capability to successfully import structural VHDL
into Designer is currently not available. HP-UX users can only import
either a structural EDIF or structural verilog netlist. This limitation
does not exist on the Sun Solaris or Microsoft Windows versions.
32483 – GCF files with macro constraints must have the constraints
in the correct relative order in the file. If the constraints are not
in the proper order, the message: " WARNING: undefined_macro" message
is generated. This warning is not displayed on previous versions of the
Designer software..
Designer HP-UX
Designer 5.0 Service Pack 1 for the HP-UX operating system is available
as an integrated installation. To obtain Designer 5.0 with Service Pack
1 for the HP-UX operating system, please contact your local Actel Sales
Representative and ask for part number DES_HP_PL_F-1YR.
