Designer v5.0 Release Notes
ProASICPLUS
The following ProASICPLUS devices are now available
in the specified mil temp plastic packages.
| Device |
Packages |
| APA300 |
208 PQFP |
456 BGA |
| APA600 |
208 PQFP |
456 BGA |
| APA1000 |
208 PQFP |
456 BGA |
Please refer to the ProASICPLUS military grade datasheet
for further details.
Axcelerator
- Axcelerator no longer supports PerPin FIFOs. Designs that used PerPin
FIFOs should be modified to remove them.
- Prototyping support for the RTAX2000s radiation tolerant devices
is available in this release. The RTAX2000s is available in the following
packages:
| Device |
Packages |
| RTAX2000S |
352 CQFP |
624 CCGA |
Please see the Online Help for
more information on each feature.
ProASIC/ProASICPLUS
Customers using ProASIC or ProASICPLUS devices should
refer to the following application note for additional information on
using Designer 5.0 with their existing designs: ProASIC
and ProASICPLUS Design-Flow Migration to Designer v5.0
MultiView Navigator
The MultiView Navigator is Actel’s new interface for design physical
design constraints and viewing. This interface includes the ChipPlanner,
PinEditor, I/O attribute editor and Netlist Viewer. The MultiView Navigator
allows for improved crossprobing between these tools, as well as introducing
new “undo/redo” and find capabilities.
ChipPlanner
ChipPlanner is Actel’s new graphical floorplanning tool for the
ProASIC, ProASICPLUS, and Axcelerator families.
For ProASICPLUS customers with existing constraints,
please refer to the following application note: Keeping
Existing Constraints when Using the ChipPlanner with ProASICPLUS
Reports
20503 - “File” > “Find”, and “File” > “Find
Next” have been added to the reports interface.
Timer
For users of the ProASIC and ProASICPLUS devices,
a new tech brief is available that discusses using Timer with the ProASIC
and ProASICPLUS devices.
ACTgen
22774 - When generating a PLL for ProASICPLUS in ACTgen,
a secondary frequency was displayed when defaults are chosen even though
there is no real secondary frequency. This issue has been resolved.
26110 – ACTgen now accepts spaces in the project name and project
path.
Libraries
23906 - Vital libraries no longer require that the entity be compiled
before the architecture.
Import
24264 - If a file is referenced for import in the GCF using a “/” character,
compile now recognizes the “/” character and can read the
file.
Device Selection Wizard
26972 - Changing the default I/O standard in an existing SX-A design
will no longer invalidate layout.
PinEdit
27399 - PinEdit now shows the I/O tile coordinates for ProASICPLUS devices.
Click any of the links below for a description and workaround.
ChipPlanner
27864 - Changing the target device after using the ChipPlanner with
a ProASICPLUS device may cause Compile to stall.
27864 - Changing the device after setting floorplanning constraints
in ChipPlanner may cause Designer to stop functioning. To change devices,
re-import the netlist into a new design.
28117
- Changing the name of a region does not take affect until after you
click the “OK” button.
27347
- The ChipPlanner does not warn you if the same macro is assigned to
two separate regions. However, layout detects this error and fails.
29980 - ChipPlanner may show the status of some routed nets as unrouted
in the Axcelerator device even after layout has succeeded. The nets are
routed and the status message is in error. If layout succeeds, the device
has been routed.
29548 - When viewing fan-in nets leading to RAM elements in the ChipPlanner,
some nets may not be drawn all the way to the memory and seem to terminate
before touching the RAM. This is a display issue and the nets are actually
connected to the memory block.
29400 - In the hierarchy display, selecting a block shows the selection
of the elements of that block but not the block itself. Also, assigning
or locking the block shows the elements of that block as assigned, but
the block itself does not show as assigned or locked even though the
block and its contents are assigned.
PinEditor
29753 - If you use the APA075-TQ144 device and package combination and
use pin 30 on this package, you must modify your last_placement.gcf file
before you open your design in v5.0. The R1-2003 SP3 update assigns pin
30 on this package to an invalid location and this assignment must be
deleted in the last_placement.gcf for your ProASICPLUS design.
Failure to do so causes Designer to display an error when you open your
ADB design file.
ACTgen
23114 - The valid width range for a standard barrel shifter is 2 to
63, and the valid width range for a shift register and a pipe-lined barrel
shifter is 2 to 99.
Scripting
23034
- Due to limitations in the Tcl language syntax, bracket characters “[“ and “]” commonly
used in bus notation must be escaped.
24270 – The
Tcl processor does not create a new line for any “put” command
with an empty string.
Import
20984 - Do not import the "lastplcmnt.gcf" file for incremental
layout. Please export the GCF file and use it instead.
29802
- Designer may exit prematurely if an empty region is specified in
a GCF file contains a RAM location.
I/O Attribute Editor
29876 - The Edit > Copy option from the tools menu will not allow
users to copy and paste data from the I/O Attribute Editor.
SmartPower
28172
- The clock frequency must be set before the data toggle rate. Failure
to do so causes SmartPower to dispay the incorrect data toggle rate.
30096
- Some UNIX users may see the message "Invalid imagelist handle
passed to API" displayed in the console window when starting SmartPower.
You can ignore this message.
Layout
29807 - Do not use the memory.gcf file generated by ACTgen. This file
is now obsolete and importing this file causes layout to fail.
BSDL
27234
- Attempting to export a BSDL file may cause Designer to display an
error.
