ProASIC/ProASICPLUS
PinEdit:
If the input signal for PLL comes from an external pin, older versions
of Designer will modify the location of Pin if you don't use the dedicated
global pins. This has been fixed.
We had an issue with Designer crashing on HP-UX when PinEdit is invoked
after compile for ProASIC and ProASICPLUS family.
This has been fixed.
We have fixed an issue that occurred if, following a successful
layout, a pin was manually unassigned using PinEdit. A subsequent re-run
of compile and layout resulted in the placer crashing with the following
error:
NOTE [Cannot_fit_IOs]:
Number IOs=181 Available IO positions=171
Cannot fit IOs.
SYSTEM [Task_have_been_terminated]:
Placer have been terminated. Result has not been saved.
SYSTEM [run_time_error]:
Error has been detected. Placer not finished correctly.
This issue has been fixed in the current version of Designer.
Timer:
This service pack resolves an issue with sdf file generation for global
macros that only happens if you have the following macros in your netlist:
GLIB: Independent input buffer only
You will see the following error during sdf file generation:
Error: at line 107, SetPropagationDelay returned S_FALSE.
Error occurred while processing SDF file, reader terminated.
Error reading SDF file ./glib-am.sdf
Error: The command export failed with error code 0x1
SDF GENERATION FAILED
This has been fixed in the current version of Designer.
We have modified the header information in the Timer Report for external
setup and hold time to more clearly describe it's function.
Schematic in Timer was showing incorrect port connections
for RAMs and FIFOs. This has been corrected.
ACTgen:
ACTgen was saving macros in /<Designer_install>/bin
directory, but not saving any ACTgen macro in that folder. This
has been fixed and ACTgen will not longer attempt to write to the /<Designer_install>/bin
directory.
Some of the macros generated from ACTgen for ProASICPLUS family
did not have a library statement in the VHDL netlist. This issue has
been fixed.
RAM/FIFO:
We fixed an issue with the ProASIC Verilog model for RAM. With asynchronous
read configuration, post layout simulation shows different behavior
than post_synthesis simulation. The Verilog library model has been
updated to correct this problem.
In previous versions of Designer, ProASIC and ProASICPLUS Synopsys
libraries for RAM are missing some port names or the port names are
misspelled. These incorrect and missing port names have been corrected:
RAM256X9SSTP, RAM256X9SST, RAM256X9SSR, RAM256X9SAP, RAM256X9SA
- missing WCLKS
RAM256X9SSRP - missing WCLKS and RCLKS
FIFO256x9SAP, FIFO256x9AST, FIFO256x9ASRP, FIFO256x9ASR, FIFO256x9ASTP,
FIFO256x9AA, FIFO256x9SA- PARODD spelled as PARROD.
Layout:
The GCF constraint for assigning signals to global spines, for APA150,
APA300, and APA450 families fails in previous versions of Designer
during compile. For example, if CLK1_c and CLK2_c have been assigned
to T1 and T3 using the following
constraints:
dont_fix_globals;
use_global T1 CLK1_c ;
use_global T3 CLK3_c ;
The compile fails with the following error:
PROBLEM [invalid_spine]:
Global spine T1 in file
E:\test\global_spines\six_clock\designer\spine_1.gcf, line 4
is invalid.
Valid spines are T1 to T2012780752 and B1 to
B2012780752.
PROBLEM [invalid_spine]:
Global spine T3 in file
E:\test\global_spines\six_clock\designer\spine_1.gcf, line 6
is invalid.
Valid spines are T1 to T2012780752 and B1 to
B2012780752.
This issue has been fixed.
The overlapping region constraints are now supported for ProASIC
and ProASICPLUS families.
Designer will now report all un-routed nets in the log window if
it fails to route all nets for an antifuse device.
Compile:
Compile is grayed out under "Options" menu for ProASIC
and ProASICPLUS families, because it is not required
for the ProASIC and ProASICPLUS families.
In some cases, Designer reports were not showing the correct
number of constraints applied. For example, if you had the following
constraints:
----------------------------------
create_clock -period 8.0 clk;
set_input_to_register_delay 10 -from *;
set_register_to_output_delay 10 -to *;
set_location (1,1 20,16) *;
After compile, the Designer log will show:
-------
Constraints processed:
IO constraints: 0
Path constraints: 0
Placement constraints: 1
Net constraints: 0
Timing constraints: 2
Only the report summary was incorrect, layout does take the constraints
into consideration. The report has been corrected.
General Updates
In order to allow third party software derive device and package
information from the STAPL file, this file now includes the package
type in the note field.
The header for ProASIC and ProASICPLUS VITAL library
has been updated to show the proper release information as shown below:
Actel Vital 95 library for R2-2001 release.
Created by the Synopsys Library Compiler 1999.10-4
Change in APA150, APA300, APA450, and APA600 Package Pins
There was a problem in Designer with the package pins for the following:
descriptions for all APA150, APA300, and APA450 package.
The following pins are affected:
| Device |
Package |
Pins |
| APA150 |
456 FBGA |
AC6 AC7 |
| |
256 FBGA |
R1 R2 |
| |
208 PQFP |
54
55 |
| |
144 FBGA |
M2 K4 |
| Device |
Package |
Pins |
| APA300 |
456 FBGA |
D8 C8 |
| |
256 FBGA |
B3 A2 |
| |
208 PQFP |
205 204 |
| |
144 FBGA |
A3 D5 |
| Device |
Package |
Pins |
| APA450 |
456 FBGA |
B4 C5 |
| |
256 FBGA |
B2 B3 |
| |
208 PQFP |
205 204 |
| |
144 FBGA |
A2 B3 |
If you don't use the affected pins, you may proceed with installing
SP4.
However, if you have used these pins in your existing design and want
to preserve the pin asssignments you must do the following
BEFORE installing SP4:
Identify the ports connected to the affected pins using
R2-2001 SP3 (use PinEdit).
Open last_placement.gcf (generated from R2-2001 SP3) from the <design.dtf> directory
and delete the two lines containing the I/O locations for these ports.
Globally replace the string "set_initial" with "set" in
this last_placement.gcf file and add any additional user constraints
that you have for your design to this constraint file (last_placement.gcf)
to get a single gcf file.
Install R2-2001 SP4.
Start new design with R2-01 SP4 and import the original netlist for
your design and then import this modified
last_placement.gcf.
Run Compile and Layout.
Check and compare IO placement in PinEdit. It should be the same as
in R2-2001 SP3 except for the two pins.
Timing in SP4 may not be identical to SP3.
