Designer R1-2003 Service Pack 3 Version 4.6.3.x
For Installation with Designer Version:
- Actel Designer R1-2003, Version 4.6.0.38
- Actel Designer R1-2003 SP1, Version 4.6.1.22
- Actel Designer R1-2003 SP2, Version 4.6.2.10
This Service Pack is not meant for use with earlier versions of the
Actel Designer Software.
MicroSoft Windows - U.S. Version
- Windows 98, Second Edition (except APA750 and APA1000)
- Windows NT 4.0 with SP6
- Windows 2000 with SP2
- Windows XP
Sun Solaris
HP-UX
Microsoft Windows 98/NT 4.0/2000/XP
- 300 MHz Pentium processor
- FAT32 or NTFS file system recommended
- 400 MB available on disk
- 128 MB system RAM
- CDROM drive
- HTML browser
- 800 x 600 video resolution
Solaris 7, 8
- Sun Ultra processor
- 400 MB available on disk
- 256 MB system RAM
- HTML browser
HP-UX 11.0
- HP processor
- 400 MB available on disk
- 256 MB system RAM
- HTML browser
Automotive
The Designer R1-2003 SP3 release introduces the new automotive version
of Actel’s 40MX and 42MX device families. In order to use these
new devices, select the “automotive” operating condition
in the Design Setup Wizard.
For a complete list of Actel’s Automotive devices, please refer
to Actel’s Automotive datasheet.
Axcelerator
Timing information for the Axcelerator devices has been updated with
additional characterized timing numbers. These new characterized numbers
provide a more accurate representation of device performance.
Due to several updates in the Axcelerator device information, customers
using the Axcelerator devices must re-run compile using the Service Pack
3 software. Layout information can be preserved by re-running layout
using the incremental locked (fixed) option.
Programming file generation for all Axcelerator devices is now enabled.
ProASICPLUS
The APA075 TQ100 device and package combination has been added.
Please see the Online Help for
more information on each feature.
Libraries
(26051) The verilog libraries for the SX-A, eX, ProASIC, ProASICPLUS,
and Axcelerator families have been updated with improved conditions to
the constraints checks. These improvements provide a more accurate representation
for simulation.
Back-Annotation
The SDF file for back-annotation now includes the Recovery and Hold
times for the asynchronous Preset and Clear signals of sequential macros.
These new timing arcs will improve the accuracy of simulation, but some
customers may notice recovery and hold messages where there were none
previously.
PinEdit
25520 -- Previous versions of the Designer software allow users to place
the DDR_IO, DDR_FIFO, or DRR_REG macros in illegal locations and complete
layout. To verify that your DRR macro placement is legal, please re-compile
the design in the Designer R1-2003 Service Pack 3 release. To preserve
your layout, please run compile using the “Incremental Fixed” option.
27806 - An issue with PinEdit allowing the user to place a BIBUF macro
within two adjacent locations of a VREF pin has been resolved. This error
would cause layout to fail. In order to ensure that your design does
not contain the illegal pin placement, please re-compile your design
using Designer R1-2003 Service Pack 3.
ACTgen
22910 - CRC macros with inverted outputs generated by ACTgen will now
pass compile in Designer.
Layout
23509 - An
issue with the extended layout script runs only in Timing Driven Mode
for NON- ProASIC, ProASICPLUS, and Axcelerator families
has been resolved.
28572 – An issue with layout losing the pre-assigned pin locations
on iterative runs on Axcelerator devices has been resolved. Pin assignments
will be preserved on iterative runs.
Compile
24629 - When
you perform a compatible change from the RT54SX-S to a compatible A54SX-A
device, if any I/O are set to CMOS in the A54SX-A device, Designer
issues an error telling the user that CMOS is not a valid standard
for the A54SX-A device.
Export
27774 - An issue with Designer on HP-UX exporting incorrect pad names
in the DCF file has been corrected.
Timing
27204 - For SX-A and eX, the RECOVERY time and REMOVAL time arcs have
been added to the following soft macros:
dpf1, dfp1_cc, dfp1a, dpf1a_cc, dfpc, dfpc_cc, dfpca, dfpca_cc, jkf2a,
jkf2b, jkf3a, jkf3b, tf1a, and tf1b
27189 - An issue with Timer using the proper recovery time data has
been corrected. Timer previously defaulted to “0ns” in SDF
for recovery time, but now uses the proper device timing data.
26717 - For SX-S devices, an issue with timer improperly reading the
output load capacitance data been corrected. The correct output load
data from the datasheet, which was accurate, has been included into the
Timer software.
26238 - An issue with the register setup time in SX-A devices not taking
the speed grade of the device into account has been corrected.
25877 - An issue with the Preset-to-Q delay path not being exported
in the SDF file for the DFP1 macro in the SX-A family has been corrected.
23750 - An issue with Timer not being able to unset a break path for
the preset/clear pin on SX-A registers has been fixed.
23748 - An issue with Timer not updating user created path sets in
SX-A with information from the Timer preferences has been fixed.
19492 - An issue with Timer displaying information that is inconsistent
with TDPR when multi-domain clocks are present in the design has been
corrected.
18371 - Automatically generated inter-domain clock constraints have
been removed since they were causing needless timing violations. Users
can create their own inter-domain constraints by adding these paths in
the path tab.
