Designer R1-2003

Thank you for choosing the Actel Designer Series R1-2003 Development Software. These release notes outline system requirments, new features and benefits, new device support, known limitations, and other information about this release.

• Supported Platforms
• Minimum System Requirements
• Installation and Licensing Instructions
• Device Support
• New Features and Enhancements
• Resolved Issues
• Known Issues and Workarounds

MicroSoft Windows - U.S. Version

• Windows 98, Second Edition (except APA750 and APA1000)
• Windows NT 4.0 with SP5 or SP6
• Windows 2000 with SP1 or SP2
• Windows XP

Sun Solaris

• Solaris 7
• Solaris 8

HP-UX

• HP-UX 11.0

Microsoft Windows 98/NT 4.0/2000/XP

• 300 MHz Pentium processor
• FAT32 or NTFS file system recommended
• 400 MB available on disk
• 128 MB system RAM
• CDROM drive
• HTML browser
• 800 x 600 video resolution

Solaris 7, 8

• Sun Ultra processor
• 400 MB available on disk
• 256 MB system RAM
• HTML browser

HP-UX 11.0

• HP processor
• 400 MB available on disk
• 256 MB system RAM
• HTML browser

Complete Installation and Licensing Instructions are included with the software.

You must have a license that matches your software version in order to run Designer vR1-2003. If you do not have a license to run software v.4.6 or above, your software will not work. Please update your license here.

ProASIC^PLUS

The -F speed grade is now available in software for ProASIC^PLUS devices. Please consult your Actel Sales representative for availability of silicon devices.

Axcelerator

The package layout for the AX500-FG484 has changed.

• The following AX500-FG484 package pins are no longer bonded to I/O:
  C10, C11, C14, AB8, AB16
• The following AX500-FG484 package pins can now only be used as single ended I/O:
  AB7, AB17, C15
  

Please verify that your package layout conforms to these changes.

If you have an existing AX500-FG484 design that use the re-assigned pins, please export the netlist and all constraint files and re-import them into a new design database to correct the pin layout. To partially preserve your pin placement, export the PDC file for the I/O and remove the pins: C10, C11, C14, AB8, AB16, AB7, AB17, C15 from the PDC file before re-importing. The pins can then be re-assigned to legal locations using PinEdit.

Please see the user guides for more information on each feature.

Timer

• Timer now supports skew analysis for ProASIC, ProASIC^PLUS, and Axcelerator Families
  
• The violation report now includes hold-time checking for ProASIC, ProASIC^PLUS, and Axcelerator Families
• Skew is now included in the analysis of the clock frequency
• The expanded path window now includes additional skew information for violation analysis
• Timer now grays out data that has been outdated by user constraints
• Constraints violations are now flagged on the summary tab
• In the summary and clock tab, you can now expand the path that is the source of the clock
• For designs with data feeding back in from a BIBUF I/O, Timer takes the feedback path into account for the reg-reg frequency calculation. This new feature may cause existing designs to show a different reg-reg frequency since this path was previously ignored. To obtain the reg-reg frequency without taking this path into account, either break the path at the enable pin of the BIBUF or set the path through the BIBUF as an exception.

APS

The APS programming software for the discontinued Activator 2 programmers is no longer installed.

SmartPower

• Now supports the ProASIC and ProASIC^PLUS families
  
• The following modifications can be saved into the design database:
• Modification of a set of pins or a clock domain. These modifications result from removing a pin from the domain or adding a new pin into the domain.
  
• Modification of frequency values of a domain


• Modification of activity (annotation) of pins
  
• Deletion of an existing set of pins or a clock domain
  
• Creation of a new set of pins or a clock domain
• Clock domains, Set-of-Pins, and annotated pins can now be included in the SmartPower text report

Extended Layout Scripts

The R1-2003 release includes enhanced, extended layout scripts. These TCL scripts force the layout to run with an extended set of parameters and enable you to optimize for a specific clock. These scripts cause an increase in layout runtime in an attempt to improve performance and routability. There are two scripts available, iterate.tcl and sh_iterate.tcl.

• iterate.tcl - This script runs from the GUI and assumes that you have successfully completed the compile stage of your design. To execute the script:

1. From the File menu, select Execute Script.
2. Browse to the Scripts directory in your Designer installation directory and select "iterate.tcl". The script runs five iterations of the extended parameter layout.
3. (Optional) To change the number of iterations, add a "-n" and the number of iterations you wish the layout to attempt in the argument box. The maximum value for iterations is 26.
4. (Optional) To specify which a clock to optimize for, add a "-c" and the name of the clock you wish the layout to optimize.
5. Click the Run button to execute the script.

• sh_iterate.tcl - This script is the command line version of the iterate.tcl script and is recommended for UNIX users. This script also requires that you have successfully compiled your design.

1. Run this script from the acttclsh shell located in the "bin" directory (in your Actel designer installation directory). This script is located in the "script" directory of the Actel installation. This script runs five iterations of the extended parameter layout.
2. (Optional) In order change the number of iterations, add a "-n" and the number of iterations you wish the layout to attempt.
3. (Optional) To specify which a clock to optimize for, add a "-c" and the name of the clock you wish the layout to optimize.

Netlist Viewer

• Netlist Viewer now allows users to switch between pre-optimized and post-optimized design netlists for the Axcelerator family
• Page navigation icons have been added to the toolbar to enable users to move across display pages in the Netlist Viewer
  

FlashLock

The FlashLock Permanent Lock feature is now enabled for the ProASIC^PLUS family.

Simulation

The ProASIC, and ProASIC^PLUS RAM simulation models in Vital and Verilog have been updated to allow preloading of memory content for simulation. Please refer to the "Preloading of ProASIC^PLUS RAM Models in Simulation Using Designer" application note.

Log Window

The new Log Window enables you to quickly differentiate between different types of messages, filter for messages, and get more details about particular errors. The new Log Window features include:

• Filtering - Tabs enable you to now see all messages, or just error, warning, or informational messages. The Output window displays all messages; the Warning window displays only messages that are categorized by Designer as warnings; the Errors window displays only messages that are categorized as errors; and the Info window displays messages that have been categorized as information only. Error and warning messages do not appear in the error or warnings tabs for ProASIC and ProASIC^PLUS designs. These messages are displayed in the output log tab.
• Colors and Symbols - Colors and symbols are used to differentiate between errors, warnings, and informational messages. A Log Window Preferences Manager allows you to select unique colors for informational, error, warning, and hyperlink text.
• Online Help - Some errors are linked to online help, where you can find more information and workarounds.

22759 - Using ACTgen for Axcelerator Designs
A problem with Axcelerator Fast Counter flags being reversed has been corrected.

22764 - Using ACTgen for ProASICPLUS Designs
ACTgen PLLs now function properly in simulation. An error in the output of ACTgen generated FIFO's has been corrected.

22480 - Using ACTgen for SX-A Designs
An issue with the almost full and almost empty flags being reversed resolved for SX-A FIFOs has been corrected.

Click any of the listed issues for a description and workaround.

ACTgen

22958 - Attempting to generate FIR-Filters with a width of 16 bits and 64 tabs may cause ACTgen to exit prematurely.

23018 - When specified from a GEN file, FIR filters always have the default value for DataMaxFo and clock frequency regardless of what was specified in the GEN file.

23280 - The accumulator for ProASICPLUS includes an ACLR pin which has an INOUT property even if no ACLR is selected for the accumulator.

23980 - For an async FIFO, if the empty flag goes low and RDB receives a rising edge (read-shift-register enabled), the read-shift-register advances by 1. Because of the unintended counter advance, the FIFO address counter is off by 1 until the read-shift-register returns to its initial state.

22845 - Register Files generated by ACTgen for SX-A have a port direction of INOUT for the Rclock pin. The Rclock pin should have an IN port direction.

22990 - Generate FIR filters for the SX-A family only from the "Basic Options" Tab. Attempting to generate a FIR filter from the "Advanced Options" tab may cause ACTgen to exit prematurely.

16038 - CRC Macros must have a width that is a power of 2. Attempting to generate a macro with a width that is not a power of 2 causes ACTgen to return an error, though it still generates a netlist. Do not use the generated netlist.

24055 - FIFOs created by ACTgen with flags must have Write Enable (WE) and Read Enable (RE). The "none" selection for the WE and RE signals are not legal for FIFOs with flags.

Compile

23481 - Compile fails if the net and the port in the netlist have the same name.

22420 - You must set register combining for Axcelerator before the compile stage.

24238 - Existing AX500-FG484 databases with pins that are no longer available in the device (as described in the Device Support section on this page) may cause the Designer software to abort prematurely.

Layout and Extended Layout

23509 - The extended layout script runs only in Timing Driven Mode for NON- ProASIC, ProASIC^PLUS, and Axcelerator families.

Reporting

23414 - Warning messages from SmartPower are only reported in the output tab.

23326 - Error and warning messages do not appear in the error or warnings tabs for ProASIC and ProASIC^PLUS designs.

23492 - In the expanded Timer window, selecting the grid and clicking Edit -> Copy does not properly copy the entire grid.

FlashLock

23531 - While the FlashLock GUI allows for a security key of 66 characters for all ProASICPLUS devices, only the largest ProASICPLUS device allows 66 characters.

SmartPower

23869 - When you open the "Create set of Pins" dialog box, move it, and then close it (in that sequence), the SmartPower GUI does not refresh properly.

23866 - SmartPower cannot accept a negative value for the ambient temperature.

24211 - For the ProASIC and ProASIC^PLUS devices, if any changes are made to the capacitance loading in PinEdit, you must close and re-open the design for the changes to be reflected in SmartPower.

Selecting the Domain tab after standard place-and-route executed from a script may cause SmartPower to exit prematurely on the HP-UX platform.

PinEdit

24460 - Do not assign a regular I/O macro to a PECL pad position.

Axcelerator

• The package layout for the AX500-FG484 has changed.

Timer

Axcelerator

• On "Register to Output" and "Input to Output" paths, Timer reports a delay that is over 1ns pessimistic.
• 23922 - Incorrect labeling in expanded path frame for setup/hold checking.

SX-A, SX-S

• 23378 - For the A54SX72A and RT54SX72S, the Timer shows three entries for each QCLKBUF used.

Simulation

Model Technologies ModelSim

• 23906 - Updates to the Vital libraries now require that the entity be compiled before the architecture.
• 24137 - The CLK2 output of the ProASIC^PLUS PLL does not produce an output in simulation.

PLLs - ProASIC^PLUS

24462 - The GL (located adjacent to GLMX), GLMX and regular I/O pins may not drive the PLL in real silicon. You can prevent this problem if you do not have fixed pin assignments and use the GL pin adjacent to the PECL pad to drive the PLL.