Designer R1-2002 Service Pack 2,

Version 4.5.2.14 for Windows and Solaris
Version 4.5.2.15 for HP-UX

For Installation with Designer Versions:

• Actel Designer R1-2002, Version 4.5.0.12
• Actel Designer R1-2002 SP1, Version 4.5.1.15

The Actel Designer R1-2002 Service Pack 2 may only be installed over Designer R1-2002 and Designer R1-2002 SP1.

• Device Support
• Software Updates
• Known Limitations and Workarounds
• Installation Instructions

ProASIC^PLUS

Device	Package
APA450	484 FBGA
APA600	484 FBGA

RT54SX72S

Updated characterized timing data.

Layout:

• Thee layout options for the ProASIC^PLUS devices have been updated.  The new interface now makes it easier for you to implement a flow using incremental placement.
  • When you select Incremental Mode "On" in the Placer Options dialog and then hit "OK", the following occurs automatically:
    • Designer copies the file last_placement.gcf to a new file initial_placement.gcf. Both files are in the design.dtf directory.
    • Designer runs Compile. Compile adds initial_placement.gcf to its constraint file list contained in master.gcf and updates the design.
    • Designer runs Layout. The incremental place option and the initial placement constraints are passed to the placer during Layout.
  • When you select Incremental Mode "Fix" in the Placer Options dialog and then hit "OK", the following occurs automatically:
    • The placer treats all initial placement (set_initial) constraints as fixed placement (set) constraints. The constraints file itself does not change. Only the placer handling of the set_initial constraints changes.

• Axcelerator Fast Placement Mode

Axcelerator now includes a fast placement mode. In this mode, the layout software delivers most of the performance of the original placement in a fraction of the time. For users who are not pushing the limits of device performance, this option will greatly reduce the runtime of layout.

Layout now provides you with the ability to select your placement effort level. This option allows you to select the effort level from 1 to 5, with 5 yielding the best results in the most time. The default value is 3.

If you are using TCL scripts, you can select the effort level by using the following command:

layout -effort_level <1-5>

• New Axcelerator Layout options
  Axcelerator users can now select the Placement and Layout options separately in the Layout options menu. 
• SX/SX-A/SX-S/eX Layout Runtime Reduction

Layout runtimes for the families mentioned above have been reduced by roughly 45% while maintaining average performance and routability.  With these new improvements, you can achieve higher performance by setting a greater TDPR effort level.  

ACTgen

• ACTgen now includes improved multipliers for the ProASIC^PLUS family of devices
  • FC Booth-1 multipliers with enhanced pipelining function are added for the ProASIC^PLUS family.

Libraries

• New multipliers have been added to the Synopsys Designware libraries for the ProASIC^PLUS family.  These updates now increase the performance of ProASIC^PLUS multipliers by 30% but also increase the size by 9%.

FlashLock

• FlashLock has been added to the ProASIC^PLUS device. Programming files for the ProASIC^PLUS can now access the FlashLock security feature of the ProASIC^PLUS device.

Timer

• The Timer GUI models the ProASIC^PLUS PLL as a register.  This allows you to analyze the signals entering the PLL as a different clock as those exiting the PLL.

 
• Post Layout numbers for ProASIC^PLUS may appear faster for some designs.  This performance increase is due to improved accuracy in the timing numbers for the ProASIC^PLUS family devices.
• New characterized timing numbers have been added for the RT54SX72S device.  With the addition of these new characterized numbers, customers can expect to see slightly different timing numbers than were reported in the previous version of software.

PinEdit

• The GLINT macro is no longer counted as an I/O in the ProASIC^PLUS devices.  GLINT is an internal macro and should not have been counted as an I/O since the I/O location can still be used as a normal I/O.

  For ProASIC devices, the GLINT will continue to be counted as an I/O since using the GLINT in the ProASIC device removes a usable I/O.

Programming

• This service pack is required to enable the Schmitt Trigger input option for the ProASIC^PLUS devices.

ACTgen

• Axcelerator
  • Attempting to generate an HSTL II or FIFO controller macro will cause ACTgen to generate errors and fail.
  • Linear Counters are only limited to the ripple counter type. Nothing will be displayed in the counter type selection box.
  • For fast-counters generated by ACTgen, the "up" counter selection will generate a down counter, and the "down" counter selection will generate an up counter.
• eX
  • ACTgen cannot currently generate the Up/Down fast balanced counter, the gray counter, or the barrel shifter.
• ProASIC^PLUS
• There are errors in the outputs of FIFO's generated by ACTgen for the ProASIC^PLUS devices.  The output data is flipped.  For example for input data of the form:
  

  A, B, C, D......

  The output is:
  

  B, A, D, C.......

• Current PLLs generated by ACTgen cannot be simulated.  Simulating these PLLs will fail in the simulator
• SX-A
  • The almost full and almost empty flags generated for SX-A FIFO's do not behave correctly.  Currently, the AEF behaves like the AAF and vice versa.
  • Register File generation in ACTgen currently generates a non-functional register file.

Compile

• Several enhancements have been added to improve Axcelerator performance, however, these changes will require that ALL Axcelerator designs prior to the R1-2002 SP2 release be recompiled.

  To preserve your current placement, run layout in incremental mode with the "fixed" option.

Layout

• Due to updates in the architecture data used for timing extraction, all ProASIC^PLUS designs must re-run the router in incremental mode.  The routing data will not be changed.

PinEdit

• In the ProASIC^PLUS family, do not assign a global signal to a GLMX pin.  Do not use these pins with general-purpose globals, only as a GLMX.  The GLMX pins are:

  	075	150	300	450	600	750	1000
  PQ208	23 135	23 135	23 135	23 135	23 135	23 135	23 135
  PG456		N2 N25	N2 N25	N2 N25	N2 N25	N2 N25	N2 N25
  TQ100	E21 W21	E21 W21
  FG144	D12 F3	D12 F3	D12 F3	D12 F3
  FG256		H2 H13	H2 H13	H2 H13	H2 H13
  FG484				L6 L16	L6 L16
  FG676					N2 P22	N2 P22
  FG896						R2 R29	R2 R29
  FG1152							U4 U31

Timer

• Constraints set on the PLL output clock can only be used for timing analysis.  These constraints will not be saved in the database and will not be used by TDPR.
• If a clock input is used only as a REFCLK to a PLL, Timer does not allow a clock constraint to be placed on that clock input.
• In the SX-A family, the exported SDF file is missing the port delays for the following Flip Flops: TF1A, TF1B, DFP1, DFP1A, JKF2A, and JKF2B.
• For the SX72A, Timer does not correctly display the cell delay for the QCLKINT macro.  The current value displayed is "0"ns.
• In the Timing Report, the "Expand Failed Paths" option will currently display no paths.
• For Axcelerator designs, Timer will report a delay that is 1.75ns greater than it should for the "Register to Out" and "In to Out" paths.

SmartPower

• Selecting the SmartPower "Domains" tab may cause Designer to crash on some designs running on the HP-UX operating systems.

Libraries

• The Vital models for the PerPin FIFO has an error which causes the overflow detection logic to be off by 1 and causes the model to cease all reads and write if the FIFO experiences an overflow or underflow condition.  The PerPin FIFO model in Verilog is correct.

The version of software that you requested is no longer the most current version available. Please download the most recent software update.

If you need this specific version of software, please contact Actel Tech Support:
Email: soc_tech@microsemi.com
Phone: 1.800.262.1060