R1-2000 Service Pack 4
This Service Pack is cumulative. It includes the contents of all previous
R1-2000 Service Packs.
For Installation with Designer Versions:
- Designer R1-2000 V4.0.0.20, Released Aug 8, 2000
- Designer R1-2000 SX16P Update, V4.0.1.1, Released Aug 29,2000
- Designer R1-2000 Service Pack 1, V4.0.2.1, Released Sep 25, 2000
- Designer R1-2000 Service Pack 2, V4.0.3.5, Released Nov 16, 2000
- Designer R1-2000 Service Pack 3, V4.0.3.6, Released Dec 20, 2000
New in SP4
- New eX Packages
CS128 - eX256
CS128 - eX128
CS128 - eX64
- RTSX32S, SX, SXA, eX - the following programming
bugs have been fixed:
- .afm file generation is disabled for all RTSX-S devices.
- The low slew IO option has been fixed for eX and SX-A devices
in this Service Pack. Please regenerate the .afm file after installing
SP4 to take advantage of the low slew option.
- The .afm file will be invalidated when you convert your design
from SX-A to RTSX-S.
Released in SP3
Attention eX64 Users:
Service Pack 3 fixes a problem in eX64 afm files that prevents Programming.
Layout and afm files generated prior to SP3 are invalid. To correct
this problem install SP3, load your design.adb file into Designer and
re-run Layout. Use the Incremental Layout option if you want
to preserve the timing of your design. Re-Verify your timing. You may
observe a slight difference.
First released in SP2, included in SP3 and
SP4
Attention A54SX72A-256BGA Users: :
Service Pack 2 contains a fix for an error related to the pin mapping
for this particular device and package. If you are designing with 54SX72A
256 FBGA package using Designer R1-2000 Version 4.0.2.1 you must re-layout
using Version 4.0.3.5 or greater.
Released in SP4
- eX:
CS128 - eX256
CS128 - eX128
CS128 - eX64
Released in SP2
- eX:
CS180 - eX256
CS49 - eX128
CS49 - eX64
Released in SP1
- eX:
TQFP 100 - eX256
AFM generation enabled
-P speed grade added
- SXA:
256 FGBA - 54SX72A
100 TQFP - 54SX32A
Enable afm generation for SX16A
-3 speed grade - SX72A packages 208 PQFP, 484 FBGA, 256 FBGA
Released in SP2
- eX:
Removed invalid macros from CAE libraries
Updated pre-layout timing values
- SXA:
Updated pre-layout timing values
- RTSXS:
Synopsys libraries added
Released in SP4
- RTSX32S, SX, SXA, eX - the following programming bugs have been
fixed:
- .afm file generation is disabled for all RTSX-S devices.
- The low slew IO option has been fixed for eX and SX-A devices
in this Service Pack. Please regenerate the .afm file after installing
SP4 to take advantage of the low slew option.
- The .afm file will be invalidated when you convert your design
from SX-A to RTSX-S.
Released in SP3
- eX64 - Corrects a problem in eX64 afm files that prevents Programming.
Layout and afm files generated prior to SP3 are invalid. To correct
this problem save your adb, install SP3 and re-run Layout using Incremewntal
Layout if you want to preserve pin assignments or timing.
Released in SP2
- 54SX72A 256 FBGA - Fixes an error related to the pin mapping. If
you are designing with 54SX72A 256 FBGA package using Designer R1-2000
Version 4.0.2.1 you must re-layout using Version 4.0.3.5 or greater.
- Actgen - Several Actgen storage registers passed data when the enable
signal was not asserted. This is resolved.
- eX - Removed invalid macros from the eX library. Refer to the R1-2000
release notes for a list.
- 54SX16P - The redundant PCI check box is removed from Device Selection
and the fuse state is now invalidated when the I/O type is changed
from TTL to PCI, or PCI to TTL. The default is PCI.
- Script - Added a warning message when script file will overwrite
script from which it was run.
- Script - Demand driven mode is disabled for Designer script.
- Timing-Driven Layout - Designer now allows Layout to proceed even
where the timing constraints seem too restrictive.
- Designer reports an error when quotes are used in the design name
and prompts you change the name.
- BSDL - Design specific BSDL files can be generated from Designer
for all SX and SX-A devices. For eX, the BSDL files can be generated
for all packages except for Chip Scale packages. To generate a design
specific BSDL, first complete the layout process for your design, then
go to the Files menu and select Export ->
Auxiliary file. From the Export window that opens, select "BSDL
Files (*.bsd) then enter a file name. Click OK to export the file.
- The maximum number of characters for an instance or net name has
been increased from 100 to 1024.
- APSW - ACT-PCHECK-FUSE is enabled only for RH and RT devices in
APSW
- APSW - APSW will not allow you to open an eX or SX-A programming
file. Programming of these devices is only supported on the Silicon
Sculptor.
Released in SP1
- SXA & RTSXS - The missing TRST pin label in Pin Edit for 208
CQFP and 256 CQFP packages has been corrected.
Released in SX16P Update
- Corrected a problem where SX16P post-layout timing date was not
displayed in Timer
