Actel

CoreConsole v1.4 Release Notes

(Oct 31, 2007)

Thank you for your interest in Actel's CoreConsole v1.4.

What's New

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Web-based update of IP database

CoreConsole v1.4 adds support for updating your IP database from the Actel web-based IP repository. CoreConsole can now seamlessly detect, download, and install new or updated IP cores that are published in the Actel web based IP repository. Now you can remain up to date with the latest Actel IP core CCZ releases simply by running CoreConsole.

By default, CoreConsole will check for new or updated IP core CCZ files in the Actel web-based IP repository at startup, alert you to any available IP for download, and guide you through the selection, download, and installation process. IP cores updates can also be fully automatic so that new IP core releases are automatically downloaded and installed in the background without any user intervention.

New or updated cores acquired in this way are available for immediate use in CoreConsole and the Libero IDE catalog. CoreConsole's Actions > Change Versions can be used to update existing designs to use updated IP cores. The CoreConsole IP update mechanism can be configured by using the Options > System Options dialog box and clicking the Updates tab.

New IP cores

CoreConsole v1.4 includes all IP cores previously shipped with CoreConsole v1.3 and CoreConsole IP Database Update v1.3.0007.0824, as well as the following updates:

System Requirements

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Supported Platforms

Microsoft Windows

  • Windows XP (XP Professional only) with SP2
  • Windows 2000 with SP4
Minimum System Requirements

Microsoft Windows 2000/XP (Professional only)

  • 1.0 GHz Pentium class processor
  • FAT32 or NTFS file system recommended
  • 400 MB available on disk
  • 128 MB system RAM
  • CDROM drive
  • HTML browser
  • 1024 x 768 video resolution

Licensing

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CoreConsole v1.4 uses the same license as CoreConsole v1.3, v1.2.1, v1.2, and v1.1. Existing users do not need to upgrade their license. If you are a new user, a license can be obtained for free from the Software Licenses and Registration System.

Known Issues and Workarounds

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Web-based update of IP database
  • When multiple versions of a core are detected in the Actel web-based IP repository, but not in your local CoreConsole IP database, the update mechanism will only show the latest version. However, you can instruct CoreConsole to display, download, and install older versions too if necessary.
  • If the New IP Cores message box appears while you are configuring a single core instance of CoreABC (or any other core with an LGI/Loose Generator Interface custom configurator) from within the Libero IDE, then click No and do not proceed with the update process, as the IP Cores Available dialog will not appear or work correctly.
  • If you use Actions > Rebuild Database immediately after launching CoreConsole, CoreConsole may inform you that certain IP cores are new even though they are already in your local IP database. If this happens, click No on the New IP Cores message box and, once the database has been reindexed, check again for updates by using the Options > System Options dialog box and clicking the Updates tab or just let CoreConsole automatically check for updates next time it is launched.
  • If you use CoreConsole to configure single core instances from within the Libero IDE, then you may find that CoreConsole does not run long enough to obtain certain large IP core CCZ updates. If this happens, then just run CoreConsole standalone or from the Libero IDE Project Flow window to allow it to download and install any outstanding updates.
Change Versions
  • IP core updates normally retain backward compatibility between the new and old core version's configuration parameter and signal names. However, sometimes this is not the case and backward compatibility is impacted. For this reason when using Change Versions to change an existing instance of a core to use a different version of the core, you should review the configuration settings and stitched connections to ensure consistency before and after carrying out this operation.
Design Generation
  • To import a design generated from CoreConsole standalone (i.e. not from within the Libero IDE) into Libero IDE:
    1. Run Libero IDE.
    2. Open or create a Libero IDE project.
    3. From the File menu, choose Import Files.
    4. Select Files of type Components (*.cxf).
    5. Browse to <CoreConsole-LiberoExportFolder>\<design-name>\
      <design-name>\<design-name>.CXF      .
    6. In CoreConsole v1.2.1 and earlier, the file generated and used to import a CoreConsole generate design was <CoreConsole-LiberoExportFolder>\<design-name>\<design-name>.CCP. Since CoreConsole v1.3 this file is no longer generated, so CoreConsole v1.3/v1.4 designs cannot be used with versions of Libero IDE earlier than v8.0.
  • If design generation fails with the error Run time error: IP_Manager::get_file() cannot create <filename>, the problem is that another application has a file open and locked, preventing CoreConsole from accessing it. A common cause is having PDF documentation generated into the <CoreConsole>\docs folder and open in Adobe Acrobat reader, preventing CoreConsole from regenerating it. (Note that some PDF readers such as Foxit Reader do not lock PDF documents in this way). To circumvent this problem, ensure that no files that CoreConsole needs to generate a design are open in any applications, and try to generate again.
  • Generating instances of the same core in different license modes (RTL, Obfuscated, or Eval) within a single Libero IDE project may lead to problems such as duplicate module/entity definitions. CoreConsole will default to using the best license available (RTL, Obfuscated, or Eval in that order), so this will not be a problem unless you manually change the license mode. If this issue occurs, then make sure that the license mode on all instances of the core in question is consistent across all CoreConsole designs/components in the Libero IDE project.
  • Some IP cores may conflict by having the same module/entity names in their RTL/Obfuscated implementation. If this happens, switching to VHDL mode for these cores may help address the problem, as the VHDL IP cores and tools flow support library packaging which helps with such "namespace" problem.
Simulation
  • When setting a specific core instance as root in order to simulate it using the provided user or verification testbench, you may need to regenerate the implementation files (by opening the configuration dialog and clicking OK) in order to ensure that the coreparameters.v[hd] file matches the core configuration; otherwise, you may get simulation errors.
Licensing
  • Actel node-locked licenses do not include the FLEXlm TS_OK option and cannot be used over Windows Remote Desktop/Terminal Services.
  • Having several license sources (files and/or floating license servers) specified in your LM_LICENSE_FILE environment variable can lead to long delays with CoreConsole starting up, reindexing the IP database, or checking licenses.
  • CoreConsole may persist certain license details to the registry and it may be necessary to manually remove HKEY_LOCAL_MACHINE\SOFTWARE\FLEXlm License Manager\ACTLMGRD_LICENSE_FILE if it causes problems (e.g. if applications using FLEXlm seem to be looking at license sources that are no longer listed in LM_LICENSE_FILE)
  • If you see the same core name listed more than once in the License Info dialog when running CoreConsole in standalone or fully integrated in Libero IDE, you have different versions of the same core instantiated in the design. To address this you should use Actions > Change Versions and upgrade any old versions of cores to their newer versions. CoreConsole will flag the inconsistent versions of cores as a validation error if you try to Save and Generate.
Stitching
  • When a single APB/AHB wrapped core is instantiated and Auto Stitch To Top Level is used to connect all signals to Top Level, the APB PCLK or AHB HCLK signals will not be driven by the generated testbench wrapper. To rectify this, disconnect the PCLK/HCLK signal from the top level and then use Auto Stitch to ensure that the testbench drives the clock signal.
  • Deleting a component instance that has an output signal driving a net connected to more than one other component instance will leave a net comprised of input/driven signals only, and you cannot directly disconnect the "dangling" input connections. To facilitate deletion of the "dangling" connections, connect from Top Level to one of the inputs and then disconnect the input signals from the net.
  • Stitching more than one slave interface of an APB or AHB bus fabric component instance may lead to problems with the connection names at the Top Level and mismatches between the generated RTL and subsystem top level CXF file.
  • When stitching complex designs, such as those containing more than one CPU/AMBA master and AMBA bus fabric configuration, auto-stitch may not cater for all possibilities and some manual stitching of the design may be required.
IP core documentation access
  • To access IP core documentation, right-click a core in the Components available for selection list, choose Generate documentation, and then browse to the files listed in the Documentation Generated message box. Alternatively, after generating a design, browse to the <CoreConsole>\docs folder for documentation on the specific core of interest to you.
  • See the Design Generation section above for information about how keeping documentation files open in another application (e.g. Acrobat Reader) may cause design generation to fail.
CoreConsole integration with Libero IDE
  • If you change the FPGA die setting in the Libero IDE project, you must re-generate any CoreConsole Components/Designs in the project for the new die setting to take effect. This applies in particular to Libero IDE projects targeting the Axcelerator FPGA family and to CoreConsole Components/Designs using CoreMP7.
  • Only CoreConsole v1.3 or later should be configured in the Libero IDE tool profile under Project > Profile > Core Configurator > CoreConsole. If, for any reason, you find that a version of CoreConsole prior to v1.3 is configured here, then reconfigure the tool profile to use CoreConsole v1.3 or later.
CoreABC
  • CoreABC v2.02/v2.1 to v2.3 upgrade issues
    • CoreABC v2.02/v2.1 is not compatible with CoreConsole v1.4 and, if used, will fail at generation time.
    • Existing designs using CoreABC v2.02/v2.1 will show CoreABC instances as Not Found.
    • To upgrade from CoreABC v2.02/v2.1 to CoreABC v2.3, right-click the CoreABC instance, choose Change Version and select CoreABC v2.3.
    • Review the CoreABC configuration to ensure that there are no validation errors and that all settings have migrated correctly.
  • CoreABC configurator Cancel issues
    • When instantiating CoreABC from the Libero IDE IP core catalog, CoreABC will be added (if it does not already exist) and (re)generated into the Libero IDE project even if Cancel is selected on the CoreABC configuration dialog.
    • If the core already existed in the Libero IDE project then the regeneration, while unnecessary, will not cause any problems.
    • If the core was added, but is not required, then select and remove it from the Libero IDE project.
  • When instantiating CoreABC from the Libero IDE IP core catalog, the configurator does not show the correct settings for HDL selection and License Selected.
    • HDL selected is always shown as Generate Verilog. However, CoreABC will be generated in the default language of the Libero IDE project.
    • License Selected always shows No Licensing Information. However, CoreABC will be generated with the best available license. If you wish to generate CoreABC with a specific license type, then you should instantiate CoreABC in a full CoreConsole design.
CoreMemCtrl
  • CoreMemCtrl v1.3 adds a new Synchronous SRAM mode configuration option that was not present in CoreMemCtrl v1.2. The options are Pipeline or Flow-through; the appropriate option will depend on the target board and the SRAM parts used.
CoreMP7
  • If you get the following error when synthesizing a CoreMP7/CoreMP7Bridge-based design, you will need to manually instantiate the required CLKINT buffer in your system top level that instantiates the CoreConsole generated subsystem top-level module/entity:
    Error: BLK010: the pin CoreMP7_00:CLK is driven by a non clock net SYSCLK_c_133. this pin must be driven by a clock net.
Core8051s
  • The memory map displayed for a APB slave peripherals in the Core8051s memory space is not accurate and displays peripherals at 0x00000nnn when they are actually at 0x0000Fnnn (e.g. 0x00000200 intead of 0x0000F200).
CoreAPB/CoreAPB3
  • CoreAPB is implemented to the AMBA 2 APB specification, while CoreAPB3 is implemented to the AMBA 3 APB specification. As such, the two are not totally interchangeable. For example, CoreAPB3 must be connected to an APB3 master (e.g. Core8051s) and not an APB 2 master (e.g. CoreABC, CoreAHB2APB etc.). APB 2 slaves can be connected to either CoreAPB or CoreAPB3, but APB 3 slaves can only be connected to CoreAPB3 since they require the connection/use of the APB 3 signals PREADY and PSLVERR.
Other IP core issues
Other issues
  • If you configure your Windows Display Settings to use non-standard font sizes or a DPI other than 96 DPI, the CoreConsole GUI may not appear correctly.

Download and Install CoreConsole v1.4

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CoreConsole is installed in the C:\CoreConsole_v1.4 by default unless otherwise specified. You can change the install folders for the CoreConsole application during the installation process. You are also allowed to specify the locations for your CoreConsole project folders (these are the folders in which your design data is stored and need not be in the same place as your CoreConsole folders). By default this are under the folder you selected to install CoreConsole in.

Underneath the folder you specified for your CoreConsole projects (e.g. <MyCCprojects>), three folders are automatically created the first time CoreConsole runs:

<MyCCprojects>\LiberoExport
<MyCCprojects>\SoftwareExport
<MyCCprojects>\ConsoleDesigns
  • LiberoExport is the folder where your designs generate the RTL implementation, and it is from here that you import into Libero IDE.
  • SoftwareExport is the folder into which any software generated is put and also the MemoryMap.html
  • ConsoleDesigns is the working folder where CoreConsole saves your project. It is not necessary for you to touch this, but it should be included in your backups.

A reference design (Reversi project) is provided with the CoreConsole v1.4 install. There are three versions of this design — Reversi and Reversi_M7, which are identical and use CoreMP7, and Reversi_M1, which uses Cortex-M1. To open one of these designs, from the File menu, choose Open. The reference design produces the Reversi demonstration that has been shown at various trade shows by Actel.

If you have older (CoreConsole v1.3, v1.2.1, v1.2, or v1.1) designs, there is an option presented during the install process to have these automatically copied to the new location. This is the recommended way of migrating designs from earlier versions of CoreConsole that are already installed.

Note: If you are migrating designs from earlier versions of CoreConsole you do not need to modify them to work properly. If you upgrade the version of components, you should verify that there is no impact on your top level RTL if the interfaces on the upgraded component have changed.

Download CoreConsole v1.4 – Windows Version (275 MB)