CoreConsole v1.3 Release Notes

(Jun 11, 2007)

Thank you for your interest in Actel's CoreConsole v1.3.

• What's New
• System Requirements
• Licensing
• Known Issues and Workarounds
• Download and Install CoreConsole v1.3

Actel Libero® Integrated Design Environment (IDE) integration

• CoreConsole v1.3 can now be configured in Libero IDE as an external Design Entry Tool using Project > Profile > Core Configurator > CoreConsole.
• Once configured in the Libero IDE Profile, CoreConsole can be invoked directly from Libero IDE in order to create and generate fully stitched designs containing multiple core instances or individual IP cores directly within the Libero IDE project.
• This obviates the need to run CoreConsole standalone and then manually import the generated design into Libero IDE, although this mode of operation is still supported.
• This also allows more than one CoreConsole design to be added to a single Libero IDE project.
• When a design created/generated by running CoreConsole standalone (not from Libero IDE) is imported into a Libero project, the entire design including the master SPIRIT/IP-XACT design files is copied into the Libero IDE project. This allows the design to be subsequently edited/regenerated within Libero IDE without the need to run CoreConsole standalone.

Improved performance

• Design generation, stitching, and database indexing are all significantly (approximately three times) faster than in previous versions of CoreConsole.
• The IP database is also reindexed automatically without the need for an exit/restart when a new IP core CCZ file is imported.

More extensive design validation

• Better checking and enforcement of consistent configuration options (in particular FPGA family/die, core version, license option) across multiple core instances in a single CoreConsole design and across multiple CoreConsole designs in a single Libero IDE project.
• Configuration dialogs no longer allow the user to save settings, if there are validation errors.
• Direct input integer validation and range checking for IP cores that support this in their configuration dialogs.

New IP cores compared to CoreConsole v1.2.1 with IP Database Update v1.2.1007.0228 applied:

• CoreABC v2.3.165
• Core429 v3.1.102
• CorePCIF v3.1
• Core1553BRM v3.0
• Core1553BRT v3.1.104
• CoreCFI v2.0
• CoreFMEE v2.0.120
• CoreMemCtrl v1.3
• Updated preview components

Supported Platforms

Microsoft Windows

• Windows XP (XP Professional only) SP2
• Windows 2000 with SP4

Minimum System Requirements

Microsoft Windows 2000/XP (Professional only)

• 1.0 GHz Pentium class processor
• FAT32 or NTFS file system recommended
• 400 MB available on disk
• 128 MB system RAM
• CDROM drive
• HTML browser
• 1024 x 768 video resolution

CoreConsole v1.3 uses the same license as CoreConsole v1.2.1, v1.2, and v1.1. Existing users do not need to upgrade their license. If you are a new user, a license can be obtained for free from the Software Licenses and Registration System.

FLEXlm Licensing will not work when running CoreConsole remotely over Windows XP Remote Desktop or Terminal Services. CoreConsole cannot be run from a network share of an installation on a remote host.

• CoreABC v2.02/v2.1 to v2.3 upgrade issues
  • CoreABC v2.02/v2.1 is not compatible with CoreConsole v1.3 and, if used, will fail at generation time.
  • Existing designs using CoreABC v2.02/v2.1 will show CoreABC instances as preview only/unlicensed.
  • To upgrade from CoreABC v2.02/v2.1 to CoreABC v2.3 right click the CoreABC instance, choose Change Version and select CoreABC v2.3.
  • Review the CoreABC configuration to ensure that there are no validation errors and that all settings have migrated correctly.

• New IP core CCZ files can only be imported by running CoreConsole standalone and not when running CoreConsole from Libero IDE.

• CoreABC configurator Cancel issues
  • When instantiating CoreABC from the Libero IDE IP core catalog, CoreABC will be added (if it does not already exist) and (re)generated into the Libero IDE project even if Cancel is selected on the CoreABC configuration dialog.
  • If the core already existed in the Libero IDE project then the regeneration, while unnecessary, will not cause any problems.
  • If the core was added, but is not required, then select and remove it from the Libero IDE project.

• CoreMemCtrl v1.3 adds a new Synchronous SRAM mode configuration option which was not present in CoreMemCtrl v1.2. The options are Pipeline or Flow-through and the appropriate one will depend on the target board and the SRAM parts used.

• Generating instances of the same core in different license modes (RTL, Obfuscated, or Eval) within a single Libero IDE project may lead to problems such as duplicate module/entity definitions. CoreConsole will default to using the best license available (RTL, Obfuscated, or Eval in that order) so this will not be a problem unless you manually change the license mode. If it does happen then make sure that the license mode on all instances of the core in question is consistent across all CoreConsole designs/components in the Libero IDE project.

• When setting a specific core instance as root in order to simulate it using the provided user or verification testbench, you may need to regenerate the implementation files (by opening the configuration dialog and clicking OK) in order to ensure that the coreparameters.v[hd] file matches the core configuration; otherwise, you may get simulation errors.

• If you see the same core name listed more than once in the License Info dialog when running CoreConsole in standalone or fully integrated in Libero IDE, you have different versions of the same core instantiated in the design. To address this you should use Actions > Change Versions and upgrade any old versions of cores to their newer versions. CoreConsole will flag the inconsistent versions of cores as a validation error if you try to Save and Generate.

• CoreConsole v1.3 generates a different folder structure compared to previous versions of CoreConsole. To import a design generated by running CoreConsole v1.3 standalone into a Libero IDE project:
  1. Run Libero IDE.
  2. Open or create a Libero IDE project.
  3. From the File menu, choose Import Files.
  4. Select Files of type Components (*.cxf).
  5. Browse to <CoreConsole-v1.3-LiberoExportFolder>\<design-name>\
     <design-name>\<design-name>.CXF.
     Previously the file selected to import a CoreConsole generate design was <CoreConsole-v1.2.1-LiberoExportFolder>\<design-name>\<design-name>.CCP.
  6. Note that CoreConsole v1.3 no longer generates a <design-name>.CCP file so CoreConsole v1.3 designs cannot be used with versions of Libero IDE earlier than v8.0.

• Only CoreConsole v1.3 or later should be configured in the Libero IDE tool profile under Project > Profile > Core Configurator > CoreConsole. If, for any reason, you find that a version of CoreConsole prior to v1.3 is configured here, then reconfigure the tool profile to use CoreConsole v1.3 or later.

• If you configure your Windows Display Settings to use non-standard font sizes or a DPI other than 96 DPI, the CoreConsole GUI may not appear correctly.

• Some IP cores may conflict by having the same module/entity names in their RTL/Obfuscated implementation. If this happens, switching to VHDL mode for these cores may help address the problem as the VHDL IP cores and tools flow support library packaging which helps with such "namespace" problem.

• License issues
  • CoreConsole only supports node-locked FLEXlm licenses for the application and IP cores.
  • Server-based floating licenses are not supported.
  • Node-locked licenses do not include the FLEXlm TS_OK option and cannot be used over Windows Remote Desktop/Terminal Services.
  • Having several license sources (files and/or floating license servers) specified in your LM_LICENSE_FILE environment variable can lead to long delays with CoreConsole starting up, reindexing the IP database, or checking licenses.
  • CoreConsole may persist certain license details to the registry and it may be necessary to manually remove HKEY_LOCAL_MACHINE\SOFTWARE\FLEXlm License Manager\ACTLMGRD_LICENSE_FILE if it causes problems (e.g. if applications using FLEXlm seem to be looking at license sources that are no longer listed in LM_LICENSE_FILE)

• When a single APB/AHB wrapped core is instantiated and Auto Stitch To Top Level is used to connect all signals to Top Level, the APB PCLK or AHB HCLK signals will not be driven by the generated testbench wrapper. To rectify this disconnect the PCLK/HCLK signal from the top level and then use Auto Stitch to ensure that the testbench drives the clock signal.

• If you get the following error when synthesizing a CoreMP7/CoreMP7Bridge-based design, you will need to manually instantiate the required CLKINT buffer in your system top level that instantiates the CoreConsole generated subsystem top-level module/entity:

Error: BLK010: the pin CoreMP7_00:CLK is driven by a non clock net SYSCLK_c_133. this pin must be driven by a clock net.

• When instantiating CoreABC from the Libero IDE IP core catalog, the configurator does not show the correct settings for HDL selection and License Selected.
  • HDL selected is always shown as Generate Verilog. However, CoreABC will be generated in the default language of the Libero IDE project.
  • License Selected always shows No Licensing Information. However, CoreABC will be generated with the best available license. If you wish to generate CoreABC with a specific license type, then you should instantiate CoreABC in a full CoreConsole design.

• If you change the FPGA die setting in the Libero IDE project, you must re-generate any CoreConsole Components/Designs in the project for the new die setting to take effect. This applies in particular to Libero IDE projects targeting the Axcelerator FPGA family and to CoreConsole Components/Designs using CoreMP7.

CoreConsole is installed in the C:\CoreConsole_v1.3 by default unless otherwise specified. You can change the install folders for the CoreConsole application during the installation process. You are also allowed to specify the locations for your CoreConsole project folders (these are the folders in which your design data is stored and need not be in the same place as your CoreConsole folders). By default this are under the folder you selected to install CoreConsole in.

Underneath the folder you specified for your CoreConsole projects (e.g. <MyCCprojects>), three folders are automatically created the first time CoreConsole runs:

<MyCCprojects>\LiberoExport
<MyCCprojects>\SoftwareExport
<MyCCprojects>\ConsoleDesigns

• LiberoExport is the folder where your designs generate the RTL implementation, and it is from here that you import into Libero IDE.
• SoftwareExport is the folder into which any software generated is put and also the MemoryMap.html
• ConsoleDesigns is the working folder where CoreConsole saves your project. It is not necessary for you to touch this, but it should be included in your backups.

A reference design (Reversi project) is provided with the CoreConsole 1.3 install. To open it, from the File menu, choose Open. The reference design produces the Reversi demonstration that has been shown at various trade shows by Actel.

If you have older (CoreConsole v1.2.1, v1.2, or v1.1) designs, there is an option presented during the install process to have these automatically copied to the new location. This is the recommended way of migrating designs from earlier versions of CoreConsole that are already installed.

Note: If you are migrating designs from earlier versions of CoreConsole you do not need to modify them to work properly. If you upgrade the version of components, you should verify that there is no impact on your top level RTL if the interfaces on the upgraded component have changed.

The version of software that you requested is no longer the most current version available. Please download the most recent software update.

If you need this specific version of software, please contact Actel Tech Support:
Email: tech@actel.com
Phone: 1.800.262.1060