CoreConsole v1.2.1 Release Notes
(Dec 5, 2006)
Thank you for your interest in Actel's CoreConsole v1.2.1.
- CoreABC
The new CoreABC programmable state machine is now available in CoreConsole.
- Generation of Memory initialization files for CoreABC
When you use CoreABC in soft mode, the memory image files necessary
for simulation are automatically imported when you import your CoreConsole
project in Libero. The memory initialization file (corresponding
to your program) is exported to <CoreConsole>\SoftwareExport\<Project>\CoreABC_nn\software.
This file can be used by SmartGen with the Init&Config mechanism
or by another processor (e.g. CoreMP7) to initialize the program
ram in CoreABC
- Generating Documentation
New Cores will be released first and made available on the Actel website
as .ccz package files. These cores are provided with their own handbooks
and documentation. The level of documentation you receive may be
dependent on your license. CoreConsole 1.2.1 enables you to generate
documents for the Core by right-clicking on the Component in the
CoreConsole Components tab and selecting Generate Documentation.
The documents for this core will be exported to <CoreConsole>\Docs\CoreName\Docs
Please ensure that you close all documents for the core before you
generate, or it will block the writing of the new docs to disk and
the generate will fail
- Dynamic Port width handling
- Complex configuration support
CoreABC is the first released example of the new style of complex configuration
support. The configuration GUI for a core can now support extended
features, like an intelligent code editor. This facility will be
used for other IP cores in the future.
- Core10100_AHBAPB – Ethernet Mac core with
AMBA interfaces available
- Fixed intermittent problem with Memory Map view (seen
in 1.2)
Supported Platforms
Microsoft Windows
- Windows XP (XP Professional only) SP2
- Windows 2000 with SP4
Minimum System Requirements
Microsoft Windows 2000/XP (Professional only)
- 1.0 GHz Pentium class processor
- FAT32 or NTFS file system recommended
- 400 MB available on disk
- 128 MB system RAM
- CDROM drive
- HTML browser
- 1024 x 768 video resolution
CoreConsole 1.2.1 uses the same license as CoreConsole 1.2 and 1.1.
Existing users do not need to upgrade their license. If you are a new
user, a license can be obtained for free from the Software
Licenses and Registration System.
FLEXlm Licensing will not work when running CoreConsole remotely over
Windows XP Remote Desktop or Terminal Services.
Known Limitations
- Effective Global settings
It is recommended that you set the Global value of a setting (e.g.
Die or Debug) on the most specific setting available: set the Die
on CoreMP7 rather than the Device Family on CoreUartApb because it
removes any ambiguity (the Family can be deduced from the Die setting,
but not vice-versa). Similarly the Debug setting should be made on
CoreMP7Bridge rather than on CoreMP7. Set your Global setting after
you have added components, so that the settings are applied. Settings
are not applied to new components added (and should be done again). The
simple rule of thumb is – set Die on CoreMP7 and Debug on CoreMP7Bridge
after you have added all components and everything will be consistent
and correct.
Note: See below if you don't have CoreMP7 in your system.
- Global settings with a CoreABC design
When CoreABC is used in your design, you should always explicitly set
FPGA Family in the CoreABC configuration scree,n even if you have
set it elsewhere. Please verify that the Family set in CoreABC is
consistent with the other cores configured in your system.
- Error report in Post-Layout Simulation
The post-layout simulation reports a setup timing violation 'error'
for the negative edge of the CoreMP7Bridge_Resetn signal. The CoreMP7
BFM timing shell has setup/hold constraints on the negative edge
of Resetn (and also DBGnTRST); as Resetn is asserted asynchronously
these timing checks are unnecessary.
The 'error' is harmless because it is due to negative edge timing constraints
on the resets, which are meaningless for asynchronous reset assertion.
- 56324 – A deleted driver for a net will not auto-stitch
back properly
If a component is deleted from a CoreConsole design that drives inputs
on more than one other component in the CoreConsole design, re-instantiating
this component and auto-stitching will not restore the deleted output
connection. The rest of the 'net' of connections (i.e. to the inputs
on the other components) remain in place. This is a rare circumstance
and the only situation where this occurs. If you find this affects
you - you can manually stitch the output in question.
- 60724 – CoreABC. Synthesis may generate incorrect results
when using Verilog and Hard mode (INSMODE=1)
When using CoreABC in a Verilog environment and Instruction Store=
Hard (Program in FPGA Tiles – INSMODE=1) Synplicity 8.5 may generate
an incorrect netlist. It is recommended the Synplicity 8.6.1 or later
is used in this case. You can download the latest software from the
Synplicity web site. This doesn't affect the VHDL flow.
- It is not recommended (or necessary) to use Rebuild Database
If you add a .ccz IP Core Package to the CoreConsole vault using Actions > Add
to Database, the recommended sequence is to Exit CoreConsole, re-start
CoreConsole and let the database rebuild itself automatically (with
the new Core). We recommend you use this automatic flow rather than
Actions > Rebuild Database, but if you do use Rebuild Database after
adding a component, please do Rebuild Database again once you have
re-started CoreConsole (it will Exit automatically).
- The automatically generated testbench expects the system clock and
reset to be named SYSCLK and NSYSRESET respectively. This only affects
the execution of the testbench. You can choose any names you like if
you edit testbench.v/vhd.
- CoreConsole 1.2.1 (and 1.2) should be used with Libero v7.2 SP1 or
newer if CoreMP7 v2.0 (or later) and CoreMP7Bridge 2.0 (or later) is
being used (in order to access the clock management support).
- When you include CoreRemap in your design, if you look at subsystem.bfm
(which you don't need to) you will see multiple memmap and include
directives. They are unnecessarily duplicated but harmless.
- CoreConsole is a single threaded application so screen updates may
stop while I/O or CPU intensive operations are in progress (e.g. generating
a design). This does not mean that CoreConsole has hung.
