CoreConsole v1.2 Release Notes
(Oct 2, 2006)
Thank you for your interest in Actel's CoreConsole v1.2.
- M7AFS1500 and M7A3P400 support
- Simplified Clock management: Clock buffering is no longer necessary
to mitigate clock skew. Consequently, it is not necessary to use a
HCLK output from CoreMP7Bridge to clock other peripherals in the system,
which simplifies clocking in the project. The Top Level SYSCLK is now
Auto-Stitched directly to components (the CoreMP7 receives its CLK
from the CoreMP7Bridge). The HCLK output is removed in CoreMP7Bridge
version 2.0 (Note – all IP Core datasheets may not have been
updated to reflect this and may ask you to connect to this signal,
please ignore this if you are using CoreMP7Bridge 2.0 or later)
- Online Help added
- Memory Map (i.e. allocating components to peripheral bus slots) can
be pre-selected and then Auto-Stitched
- Stitch to Top Level feature: Using Actions > Auto Stitch to Top
Level, it is possible to connect all (or your selected sub-set) of
un-connected signals to the Top Level for any component in your design
- Eval version support: ModelSim pre-compiled libraries now supported
for selected DirectCores (appears as Eval License)
- CoreMP7 no longer conflicts with UFROMH macro found in Libero v7.2
SP1 and higher
- DirectCore export support: When DirectCores are released as CoreConsole
IP packages, they can be added to the CoreConsole database and generated
from CoreConsole including docs, constraints and test benches.
- More detailed version information in CoreConsole About: The full
CoreConsole build number and the database checksum are now displayed
- Installer enables you to specify the location of CoreConsole project
folders (LiberoExport, SoftwareExport and ConsoleDesigns)
- Installer no longer requires the install folder to include the name ‘CoreConsole’
- Support for Single Point Setting (Globals) of key parameters in CoreConsole
projects
- Version swapping of components in a CoreConsole design
- Extended Memory Map display: Memory controllers now appear in the
memory map and information is provided on memory allocation.
- Full Auto-Stitching of all memory controllers in your design
- IP Components list display filter defaults changed
- Persistence of key filter settings
Supported Platforms
Microsoft Windows
- Windows 2000 with SP4
- Windows XP (XP Professional only) SP2
Minimum System Requirements
CoreConsole 1.2 uses the same license as CoreConsole 1.1. Existing users do not need to upgrade their license.
If you are a new user, a license can be obtained for free from Actel's
Software Licenses and Registration System.
FLEXlm Licensing will not work when running CoreConsole remotely over
Windows XP Remote Desktop or Terminal Services.
Known Limitations
- Intermittent problems with View Memory Map
On rare occasions the View Memory Map feature has been reported to
cause a CoreConsole crash. It is unlikely that you will encounter
this, but we recommend that you Save (or Save and Generate) your
project before using this feature to ensure that you do not lose
any work. Restart afterwards to ensure that everything is okay.
- Effective Global settings
It is recommended that you set the Global value of a setting (e.g.
Die or Debug) on the most specific setting available: set the Die
on CoreMP7 rather than the device family on CoreUartApb because it
removes any ambiguity as the family can be deduced from the Die setting
but not vice-versa. Similarly the Debug setting should be made on
CoreMP7Bridge rather than on CoreMP7.
Set your Global setting after you have added components, so that the
settings are applied. Settings are not applied to new components added
(and should be done again).
The simple rule of thumb is – set Die on CoreMP7 and Debug on
CoreMP7Bridge after you have added all components and everything will
be consistent and correct.
- Error report in Post-Layout Simulation
The post-layout simulation reports a setup timing violation 'error'
for the negative edge of the CoreMP7Bridge_Resetn signal. The CoreMP7
BFM timing shell has setup/hold constraints on the negative edge
of Resetn (and also DBGnTRST); as Resetn is asserted asynchronously
these timing checks are unnecessary.
The 'error' is harmless because it is due to negative edge timing constraints
on the resets, which are meaningless for asynchronous reset assertion.
- It is not recommended (or necessary) to use Rebuild Database
If you add a .ccz IP Core Package to the CoreConsole vault using Actions > Add
to Database, the recommended sequence is to exit CoreConsole, restart
CoreConsole and let the database rebuild itself automatically (with
the new Core). We recommend you use this automatic flow rather than
Actions > Rebuild Database, but if you do use Rebuild Database after
adding a component, please do Rebuild Database again once you have
re-started CoreConsole (it will exit automatically).
- The automatically generated testbench expects the system clock and
reset to be named SYSCLK and NSYSRESET respectively. This only affects
the execution of the testbench. You can choose any names you like if
you edit testbench.v/vhd.
- CoreConsole 1.2 should be used with Libero v7.2 SP1 or newer if CoreMP7
v2.0 (or later) and CoreMP7Bridge 2.0 (or later) is being used (to
access the clock management support).
- When you include CoreRemap in your design, if you look at subsystem.bfm
you will see multiple memmap and include directives. They are unnecessarily
duplicated but harmless.
- CoreConsole is a single threaded application so screen updates may
stop while I/O or CPU intensive operations are in progress (e.g. generating
a design). This does not mean that CoreConsole has hung.
