CoreConsole v1.1 Release Notes
(Apr 17, 2006)
Thank you for your interest in Actel's CoreConsole v1.1.
- Fusion M7AFS support
- CoreAI and CorePWM components added to the IP vault
- CoreAhbNvm – memory controller for on-chip Flash memory
- CoreAhbSram – memory controller for on-chip SRAM memory
- Optimized SysBASIC components – smaller Interrupt, Watchdog and Timer
- Upgraded BFM with additional features and commands for more intensive
debug
- New User Interface with filter for selecting components to display
- Memory Map generation
- Long connection name support
- Component details window for immediate summary of IP Components
- Component Version Number display
- Renamed SysBASIC IP Components for consistent display and RTL naming
- ALL connections to CoreMP7 now connect through CoreMP7Bridge
- Deleted connections 're-appearing' has been fixed
- New SoftwareExport folder for Fusion configuration software files
- Cleaner subsystem top level module RTL generation
- Configurable support for CoreMP7 debugging over FlashPro3 using Actel
SDC added to CoreMP7Bridge
- CoreConsole generated LiberoExport file (<design_name>.ccp)
provides better control of and support for target FPGA family details.
Supported Platforms
- Microsoft Windows - U.S. Version
-
- Windows 2000 with SP4
- Windows XP (Professional only) SP2
Minimum System Requirements
- Microsoft Windows 2000/XP (Professional only)
-
- 1.0 GHz Pentium class processor
- FAT32 or NTFS file system (NTFS recommended)
- 400 MB available on disk
- 128 MB system RAM
- CDROM drive
- HTML browser
- 1024 x 768 video resolution
CoreConsole 1.1 requires a new CoreConsole node-locked license and a
SysBASIC Subsystem IP license. A new license can be obtained for free from
Actel's Software
Licenses and Registration System. Licenses for previous versions of
CoreConsole will not work with the renamed SysBASIC cores.
FLEXlm Licensing will not work when running CoreConsole remotely over
Windows XP Remote Desktop or Terminal Services.
When a new license is obtained please restart CoreConsole after installing
the license. It will then automatically update its database.
Note: If any change is made to the license
file, even if it is unrelated to CoreConsole, it will detect this and
update its database. This is correct behaviour and does no harm.
- Moving between Debug and non-Debug CoreMP7
- The full CoreMP7 enables you to debug your Core. A common approach
is to develop with the Debug version first and then instantiate the
non-debug version for production hardware to minimize tile count. In
this version of CoreConsole, if you are moving from debug to non-debug
(or vice versa), you must configure the CoreMP7 component as non-debug
and re-generate. No connections need to change. If you leave the RealView
debug bus (RV_ICE_If) from the MP7Bridge to the Top Level in place
when you are using the non-debug version of the CoreMP7 you must also
configure the MP7Bridge as non-debug or synthesis returns an error
(alternatively you can delete the RealView debug bus).
- Clock Management
- M7A3P IO placement for clock is no different than for regular PA3
designs.
- The system level clock driver may directly drive the CoreMP7 black
box CLK pin (this is what happens automatically when Synplicity infers
a clock driver (CLKBUF or CLKINT) in the net that drives the CoreMP7
core CLK pin). In that case, this system level clock can only use
one of the remaining chip level globals (middle left and middle right).
The system level clock driver drives the internal CoreMP7 core clock
driver using the clock network. This introduces a skew of about 1.4
ns between the core and the system clock networks.
- The way to minimize this skew is to use the HCLK output from the
MP7Bridge. The HCLK output from the MP7Bridge is a buffered version
of the system clock and should be used to clock other peripherals
in the design that are in the same clock domain as the CoreMP7. Essentially,
there is minimal skew between the MP7Bridge HCLK output and the internal
CoreMP7 clock.
- Known Limitations
-
- CoreConsole 1.1 is not backward compatible with earlier
projects
Projects created with earlier versions of CoreConsole are not compatible
with Version 1.1 The Database has been rebuilt and is incompatible
with older components. If you do open a project from an earlier
version, all the components will appear as 'unlicensed'.
- VHDL Post-Synthesis Simulation
For the post-synthesis VHDL simulation you need to comment the
following lines in the vhdl netlist generated just after synthesis: for
all: A7SUse entity work.A7S(DEF_ARCH);
- The Component Base Address in the generated Memory Map is correct
but some of the Register descriptions may not correspond with the
information in the relevant Datasheet. The Datasheet should be
considered definitive in cases of conflict.
- The automatically generated testbench expects the system clock
and reset to be named SYSCLK and NSYSRESET respectively. This only
affects the execution of the testbench. You can choose any names
you like if you edit testbench.v/vhd.
- CoreConsole 1.1 must be used with Libero IDE v6.3 or newer. Actel
recommends Libero IDE v7.1 or newer; v7.1 is required if
you are targeting your design to M7 Fusion devices.
- CoreConsole is a single threaded application so screen updates
may stop while I/O or CPU intensive operations are in progress
(e.g. generating a design). This does not mean that CoreConsole
has hung.
