CoreConsole v1.0.1 Release Notes
(1/13/06)
Thank you for your interest in Actel's CoreConsole v1.0.1.
- VHDL generation [Verilog generation available in v1.0].
- Fast, automatic stitching of components (Auto-Stitch)
- Print and Print Preview enabled
- Scroll bars enabled in the Schematic window
- Save and Save As implemented (instead of automatic save)
- The BFM (bus functional model) testbench now automatically configures
itself to the memory map locations wherever you place your components
- Skew handling now run automatically in MP7Bridge
- De-Skewed Clock output now available from CoreConsole design
- The Design Tab has been removed
- Streamlined and simplified Generation Tab user interface
- One Click connection of the CoreMP7 to the MP7Bridge (all signals
are integrated into a single bus)
- New FROMAccess component enables reading of the FROM.
- Component Layout and user settings are saved when CoreConsole is
closed
- Licensing options have been expanded to include RTL delivery and
an Information and Selection window is available in the Generate tab
- A Generate Complete message appears when Generation is finished
- Eliminated floating Component Toolbar
- Moving between Debug and Non-Debug versions has been simplified
- Show Linked Connections option is enabled by default
Supported Platforms
Microsoft Windows - U.S. Version
- Windows 2000 with SP4
- Windows XP (Professional only) SP2
Minimum System Requirements
Microsoft Windows 2000/XP (Professional only)
- 1.0 GHz Pentium class processor
- FAT32 or NTFS file system recommended
- 400 MB available on disk
- 128 MB system RAM
- CDROM drive
- HTML browser
- 1024 x 768 video resolution
CoreConsole 1.0.1 requires a current CoreConsole node-locked license
and a Subsystem IP license.
- Moving between Debug and non-Debug CoreMP7
- The full CoreMP7 enables you to debug your Core. A common approach
is to develop with the Debug version first and then instantiate the
non-debug version for production hardware to minimize tile count. In
this version of CoreConsole, if you are moving from debug to non-debug
(or vice versa), you must configure the CoreMP7 component as non-debug
and re-generate; no connections need to change. If you leave the RealView
debug bus (RV_ICE_If) from the MP7Bridge to the Top Level in place
when you are using the non-debug version of the CoreMP7 you must also
configure the MP7Bridge as non-debug or Designer returns an error (alternatively
you can delete the Realview debug bus).
- Clock Management
-
- M7A3P I/O placement for clock is no different than for regular
PA3 designs.
- The system level clock driver may directly drive the CoreMP7
black box CLK pin (this is what happens automatically when Synplicity
infers a clock driver (CLKBUF or CLKINT) in the net that drives
the CoreMP7 core CLK pin). In that case, this system level clock
can only use one of the remaining chip level globals (middle left
and middle right). The system level clock driver drives the internal
CoreMP7 core clock driver using the clock network. This introduces
a skew of about 1.4ns between the core and the system clock networks.
- The way to minimize this skew is to use the HCLK output from
the MP7Bridge. The HCLK output from the MP7Bridge is a buffered
version of the system clock and should be used to clock other peripherals
in the design which are in the same clock domain as the CoreMP7.
Essentially, there is minimal skew between the MP7Bridge HCLK output
and the internal CoreMP7 clock.
- Known Limitations
-
- The automatically generated testbench expects the system clock
and reset to be named SYSCLK and NSYSRESET respectively. This only
affects the execution of the testbench. You can choose any names
you like if you edit testbench.v/vhd.
- CoreConsole 1.0.1 must be used with Libero v7.0 or newer.
