CoreConsole v1.0 Release Notes
(Nov 2, 2005)
Thank you for your interest in Actel's CoreConsole v1.0.
- M7A3P250, M7A3PE600, M7A3P1000 support. This release
provides CoreMP7 (both debug and non-debug) support for the M7A3P250,
M7A3PE600 and M7A3P1000 devices.
- CoreMP7 testbench generation. This release will
generate a testbench to simulate the CoreMP7 core. You can easily extend
the testbench to simulate the entire design.
- CoreMP7 BFM generation. This release generates a
.BFM file for simulation of the CoreMP7 core.
Supported Platforms
Microsoft Windows - U.S. Version
- Windows 2000 with SP4
- Windows XP (XP Professional only) SP2
Minimum System Requirements
Microsoft Windows 2000/XP (Professional only)
- 1.0 GHz Pentium class processor
- FAT32 or NTFS file system recommended
- 400 MB available on disk
- 128 MB system RAM
- CDROM drive
- HTML browser
- 1024 x 768 video resolution
Moving between Debug and non-Debug CoreMP7
The full CoreMP7 enables you to debug your Core. A common approach is
to develop with the Debug version first and then instantiate the non-debug
version for production hardware to minimize tile count. In the current
version of CoreConsole, if you are moving from debug to non-debug,
you must delete the CoreMP7 Debug component in the design and replace
it with the non debug component. This is straightforward as there are
few connections involved. The RealView debug bus (RV_ICE_If) from the
MP7Bridge to the Top Level should also be deleted if it is connected.
Clock Management
- M7A3P IO placement for clock is no different than for regular PA3
designs.
- Users/Synthesis instantiate a CLKBUF (IO hardwired to CLK driver)
in their design. The locations where the CLKBUF can be placed are
described in the package sections of the datasheet.
- Users/Synthesis instantiate a CLKINT (CLK driver) in their design.
Then every IO on the chip can drive the CLK driver (regular routing).
You are responsible for finding an IO that is closed to the CLK driver
to minimize the delay on the clock network.
- The system level clock driver may directly drive the CoreMP7 black
box CLK pin (this is what happens automatically when Synplicity infers
a clock driver (CLKBUF or CLKINT) in the net that drives the CoreMP7
core CLK pin). In that case, this system level clock can only use
one of the remaining chip level globals (middle left and middle right).
The system level clock driver drives the internal CoreMP7 core clock
driver using the clock network. This introduces a skew of about 1.4ns
between the core and the system clock networks.
- The way to minimize this skew is to hand-edit the top-level netlist
in such a way that the system level clock driver (must be CLKINT
in this case) and the internal CoreMP7 core CLK driver are parallel
clock networks (driven by the same net). Then you can manually place
the system level clock driver in the same CCC (clock conditioning
circuit) where the internal CoreMP7 clock driver has been placed.
In that case, you must place the IO or the core tile that drives
the CLK drivers in the vicinity of the CCC to minimize the clock
network delay.
Known Limitations
- CoreConsole Release 1.0 generates Verilog projects ONLY
- The layout of components on the Design Window and any Options selected
are NOT saved when you exit CoreConsole
- There are no scroll bars in the Design Window in CoreConsole and
it can not be made larger in the current version. This can sometimes
make working with large designs difficult. If you are running out
of space, you can undock the Design Manager window using View > Float\Dock
Design Manager which will provide a larger workspace.
- The automatically generated testbench expects the system clock
and reset to be named SYSCLK and NSYSRESET respectively. This only
affects the execution of the testbench. You can choose any names
you like if you edit testbench.v.
- The BFM (bus functional model) test script generated by CoreConsole
is a static skeleton script and does not update automatically to
reflect the configuration in the CoreConsole Project. To use the
BFM facility (other than the reference one or ones with the UART
at APB slot 3) you will need to edit and extend the script as described
in the CoreMP7 User Guide.
- The toolbar that appears when you float over a component on the
CoreConsole Design Window will appear above any applications that
are on top of CoreConsole subsequently.
- There is no Print facility in this version of CoreConsole.
- The Generate Results options (HDL, CoreMP7, Test, and Report) in
the Generate tab are not functional and should be left checked. The
full design will be generated each time.
- When Generating, no hourglass is displayed during the delay while
the CoreMP7 is being generated. Generation is complete when all progress
bars have gone to 100%.
- CoreConsole 1.0 must be use with Libero v6.3 or newer.
