Design Examples

Design examples offer innovative ideas for Actel FPGA applications and help users create designs that utilize the many advantages of Actel's devices. Actel's design examples are available for immediate download and are always free of charge.

	32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note  Design File (ZIP, 1.2 MB, 07/04)		655 KB	7/2004	Click on the to rate this document
	Configuring CorePWM Using RTL Blocks App Note  Verilog Design Files (ZIP, 2 KB, 09/06) VHDL Design Files (ZIP, 2 KB, 09/06)		201 KB	9/2006	Click on the to rate this document
	Configuring SRAM FPGAs Using Actel Fusion App Note  SPI SRAM Configuration Design Files (ZIP, 6.4 MB, 09/07) Fusion Master Serial Design Files (ZIP, 1.5 MB, 09/07)		341 KB	9/2007	Click on the to rate this document
	Context Save and Reload App Note  Design Files (ZIP, 5.4 KB, 06/06)		1.0 MB	6/2006	Click on the to rate this document
	Designing a MIL-STD-1553 System Using Core1553 and Core8051 App Note  VHDL: Design Files - SFR (ZIP, 6 KB, 1/05) Design Files - direct memory access (ZIP, 13 KB, 4/05) Verilog: Design Files - SFR (ZIP, 6 KB, 1/05) Design Files - direct memory access (ZIP, 11 KB, 4/05)		139 KB	4/2005	Click on the to rate this document
	Designing a SuperClock with an Axcelerator Device App Note  Design File (ZIP, 130 KB, 09/04)		417 KB	9/2004	Click on the to rate this document
	Device Serialization for ProASICPLUS Devices App Note  Design Files (ZIP, 203 KB, 8/05)		108 KB	8/2005	Click on the to rate this document
	Embedded SRAM Initialization Using External Serial EEPROM App Note  Design Files (ZIP, 14.5 KB, 1/05)		96 KB	1/2005	Click on the to rate this document
	Frequency Fine Tuning and Clock Dithering Using Actel FPGA Devices App Note  Verilog Design Files (ZIP, 9 KB, 08/05) VHDL Design Files (ZIP, 9 KB, 08/05)		198 KB	8/2005	Click on the to rate this document
	Fusion Handbook  Design File (ZIP, 3 KB, Nov 30)		4.0 MB	12/2007	Click on the to rate this document
	Fusion Power Sequencing and Ramp-Rate Control App Note  Design Files (ZIP, 3.1 MB, 09/06)		558 KB	9/2006	Click on the to rate this document
	How To Use UJTAG App Note  Design Files - UJTAG (ZIP, 207 KB)		157 KB	7/2005	Click on the to rate this document
	Implementation of the SpaceWire Clock Recovery Logic in Actel RTAX-S Devices App Note  Design File (ZIP, 86 KB, 08/07) Timing Analysis (XLS, 73 KB, 08/07)		358 KB	8/2007	Click on the to rate this document
	Implementing Multi-Port Memories in Axcelerator Devices App Note  Source Code (ZIP, 12 KB, 07/04)		190 KB	7/2003	Click on the to rate this document
	Implementing Multi-Port Memories in ProASICPLUS Devices App Note  Source Code (ZIP, 10 KB, 07/04)		186 KB	7/2003	Click on the to rate this document
	Laser Range Finder Using Actel’s Axcelerator FPGA App Note  Design File (ZIP, 345 KB, 07/04)		1.5 MB	7/2004	Click on the to rate this document
	Macro Constraint Usage in ProASICPLUS® Design Flow App Note  Design Files (ZIP, 270 KB)		467 KB	1/2006	Click on the to rate this document
	Multi-Channel Analog Voltage Comparator in Fusion FPGAs  VHDL Design Files (ZIP, 3.2 MB, 01/07) Verilog Design Files (ZIP, 1.5 MB, 01/07)		172 KB	1/2007	Click on the to rate this document
	Real-Time Calendar Applications in Actel Fusion Devices App Note  Design Files (ZIP, 3.2 MB, 06/06)		350 KB	6/2006	Click on the to rate this document
	Simulating SEU Events in EDAC RAM App Note  Design File (ZIP, 582 KB, 08/07)		1.8 MB	8/2007	Click on the to rate this document
	Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.1 and Older EDAC Core from Libero IDE v7.1 or Earlier (ZIP, 41KB, 07/04)		250 KB	7/2006	Click on the to rate this document
	Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.2 and Newer EDAC Core from Libero IDE v7.2 (ZIP, 45 KB, 06/06)		704 KB	2/2008	Click on the to rate this document