To view the corresponding available BSDL models for Designer v8.3 released on 3/31/2008, please choose one of the following FPGA families:

ACT 1 / ACT 2 / ACT 3 / 1200XL: The BSDL for these devices are not available as these families do not support JTAG Boundary Scan.

For more information, please review the Actel BSDL Files Format Description application note.

Notes

• The BSDL files contained herein are Generic BSDL only. The Actel Designer software currently supports the exporting of Design-Specific BSDL for the Fusion, IGLOO, and ProASIC3L, ProASIC3, ProASIC^PLUS, ProASIC, SX-A, SX, eX, RTSX-S and RTSX families.
• All BSDL files are syntax checked using Agilent Technologies syntax checker tool.