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1. What is Silicon Explorer II?
The Silicon Explorer II is Actel's proprietary real-time FPGA debug tool. Users have access to 100% of the internal nets of the Actel FPGA while the device is operating in a prototype or a production system. Users can select any net and probe two nodes at a time without changing the placement and routing, or using any additional resource. Moreover, the timing of the design does not change when selecting new nodes to probe.
2. What's different between Silicon Explorer I and Silicon Explorer II?
The first version of Silicon Explorer was designed to only support 3.3 V and 5.0 V devices. Also, it takes its power from the board causing potential limitations when sampling at high frequencies. Silicon Explorer II has its own external power supply. This allows the Silicon Explorer II to operate correctly on devices which utilize 2.5 V power supplies, and eliminates the power burden on the board. Other new features include four-levels of triggering for each signal, decompression on download to speed up response time and system acquisition rates up to 100 MHz
3. Can I use the Silicon Explorer II on a laptop?
This is an excellent way to use the Silicon Explorer II! The Silicon Explorer II connects to a PC through a serial port. As long as a serial port is available on your laptop, you can have the ultimate portable debug solution. And remember, the Silicon Explorer II doesn't get its power from the PC, so you can even run the laptop on battery power.
4. Does the Silicon Explorer probe circuitry require the use of additional internal device resources?
No, this is one of the major benefits of the debugging system. Each Actel anitfuse FPGA has built-in, dedicated circuitry just for probing purposes. The Silicon Explorer does not require any logic cells or routing when probing the device. Additionally, Silicon Explorer does not require or sacrifice device I/Os. On SX-A and eX devices, the JTAG pins are used to control probing. On the older families, special probe pins are used for probing. Regardless of the device, all of the probe pins can be used as user I/O except for the MODE and TMS pins. Once the device enters probe mode, the I/Os switch to the probe functionality. Actel recommends not using these pins as inputs, as they will not be available as inputs during probe mode.
5. Is there a way that to disable probing capability for security reasons?
Yes, by programming the security feature on the Actel FPGA, the built-in probe circuitry is permanently disabled.
6. What are features of the software provided with Silicon Explorer II?
Silicon Explorer II comes with software that emulates an 18-channel logic analyzer. Two channels are used to monitor 2 internal nodes, and additional 16 channels are available to probe additional external signals. Moreover, the software allows the user to set multi-level triggering schemes for each channel, multiple cursors, to filter through the design internal nets, to define busses, and many other features commonly available in very expensive systems. The system will also allow you to sample data up to 100MHz, verify the checksum of your device while it is on the board, and the newest feature is cross probing with Actel's ChipEdit tool.
7. What is cross probing?
This new feature introduced in Actel's
Designer Series R1-2001 Release establishes communication
between Actel's Timer, ChipEdit and Silicon Explorer for a complete
debug loop. While evaluating the timing of critical paths in
Timer, ChipEdit highlights automatically the placement of modules
in these paths allowing observability of the relative placement
of logic cells. From ChipEdit, users can call up the highlighted
nets in Silicon Explorer to observe their real time values.
8. How can users get Silicon Explorer II probe pilot and the associated software?
For the Silicon Explorer II probe pilot, please contact your
local Actel
sales office. Customers are kindly invited to download the
latest
Silicon Explorer software from Actel's website.
