Actel's Libero IDE Delivers Unmatched Value, Flexibility and Efficiency for Complex FPGA-Based Designs
New Static Timing Analysis Engine and Expanded
Third-Party Support Enable Designers to Meet Timing Closure and Achieve
Higher Performance
MOUNTAIN VIEW, Calif., July 11, 2005 —
Detailing
significant new functionality for design analysis and timing closure,
Actel Corporation (Nasdaq: ACTL) today introduced its Libero version
6.2 Integrated Design Environment (IDE), which integrates best-in-class
design tools to enable field-programmable gate array (FPGA) designers
to achieve the highest results in terms of quality, efficiency and functionality.
With Libero 6.2, Actel unveils its new SmartTime static timing analysis
environment, enabling customers to analyze and manage timing constraints,
perform advanced timing verification, and ensure predictable timing closure
through a tight integration with timing-driven place and route. In this
edition of Libero, Actel and Mentor have extended their partnership to
provide Mentor Graphics' world-class ModelSim AE simulation as
an integral part of the Libero "Gold" package, which is now
available to all Actel customers free of charge. In addition, the Libero
6.2 IDE includes enhanced synthesis capabilities from Synplicity and
physical synthesis features from Magma Design Automation. Further, Libero
now runs on Linux and Solaris platforms.
"With our internally engineered tools and third-party EDA solutions,
Actel combines the best of both worlds to deliver new environments and
methodologies that help users meet their design objectives easily and
in a timely manner," said Saloni Howard-Sarin, director of antifuse
and tools marketing at Actel. "This new version of our Libero IDE
includes significant new functionality for design analysis and timing
closure. Users are able to apply constraints to their designs, manage
and analyze the effects of those constraints, and drive their designs
efficiently to timing closure, while achieving higher performance."
SmartTime Static Timing Analysis Engine
SmartTime is a powerful new multi-view product developed by Actel to
help designers perform detailed timing analysis and quickly determine
the steps necessary to achieve design closure. The SmartTime Constraints
Editor view enables users to list, edit and create precise timing constraints.
It includes a graphical user interface with visual dialogs that guide
users toward capturing their timing requirements and timing exceptions
correctly. Another view, the SmartTime Analyzer, allows designers to
perform per-clock-domain minimum and maximum timing analysis, and provides
inter-clock domain analysis capabilities. The tool simplifies the analysis
process by enabling designers to track paths with timing violations quickly.
Designers can then directly set specific timing exceptions on the violating
paths to tighten or relax the requirements and quickly iterate toward
timing closure. More information on SmartTime and Libero IDE 6.2 is available
at http://www.actel.com .
Actel and Mentor Deliver Unprecedented Value
Mentor Graphics' ModelSim is a leading Windows-based simulator
for VHDL, Verilog or mixed-language simulation environments. The integrated
ModelSim verification and debug environment, which helps designers
locate bugs faster, is being offered with unlimited availability to all
Actel customers for the first time.
"Actel is delivering unprecedented value by integrating our world-class
ModelSim solution within the baseline Libero 6.2 Integrated Design
Environment," stated John Lenyo, director of product marketing for
ModelSim at Mentor Graphics. "Actel's customers can get
started quickly with our intuitive GUI, which makes it easy to view and
access the powerful capabilities that combine high performance with ease
of use."
Enhanced Third-party Tool Support
Synplicity's industry-leading Synplify FPGA synthesis software offers
a new capability to forward annotate Synopsys Design Constraints (SDC)
and physical constraints, enabling the Libero 6.2 IDE to import user-defined
constraints automatically then manage, track and pass them forward to
design implementation, enabling designers to meet timing closure rapidly.
In addition, the software now includes critical path resynthesis to improve
quality of results (QoR) for designs based on Actel's Axcelerator family
of FPGAs.
"We have maintained an exceptionally strong relationship with Actel
over the years and we're proud of our track record of delivering consistently-improving
tools for productivity and quality of results to our mutual customers," said
Jeff Garrison, director of marketing for FPGA products at Synplicity. "As
a key component of the Libero IDE, the Synplify software will give our
joint customers confidence that they can push the performance of advanced
FPGAs like Axcelerator and still comfortably meet their time-to-market
objectives."
Magma Design Automation's PALACE physical synthesis software now also
provides support for Actel's Axcelerator family. The fully automated
PALACE software features advanced technologies such as multi-clock retiming,
architecture-specific mapping, and constraint-driven and placement-guided
optimization.
"Our fully automated PALACE software tool provides at least a one
speed-grade performance advantage over other PLD synthesis tools on the
market," stated Behrooz Zahiri, director of marketing at Magma Design
Automation. "Designers using our PALACE tool with their Actel Axcelerator-based
designs can expect to see at least a ten percent improvement in speed,
allowing users to maximize performance or drop to a lower speed-grade
device to save costs, while still meeting performance goals."
Pricing and Availability
The Actel Libero 6.2 IDE is available in a Platinum edition on Windows
and Unix platforms, which sell for $2495 and $4995 respectively. Libero
6.2 IDE is available also on Windows in a Gold edition, which is free.
All editions are one-year renewable licenses. For further information
about pricing and availability, please contact Actel.
About the Libero Integrated Design Environment
Actel's Libero 6.2 IDE offers best-in-class tools from EDA leaders,
such as Magma, Mentor Graphics, SynaptiCAD and Synplicity, and custom-developed
tools from Actel integrated into a single FPGA development package. The
Libero tool suite supports mixed-mode design entry input, giving designers
the choice of mixing either high-level VHDL or Verilog HDL language blocks
with schematic modules in a design.
About Actel
Actel Corporation is a supplier of innovative
programmable logic solutions, including field-programmable gate arrays
(FPGAs) based on antifuse and flash technologies, high-performance intellectual
property (IP) cores, software development tools and design services,
targeted for the high-speed communications, application-specific integrated
circuit (ASIC) replacement and radiation-tolerant markets. Founded in
1985, Actel employs more than 500 people worldwide. The Company is traded
on the Nasdaq National Market under the symbol ACTL and is headquartered
at 2061 Stierlin Court, Mountain View, CA, 94043-4655. Telephone: 888-99-ACTEL
(992-2835). Internet: http://www.actel.com.
Contact: Stephanie Mrus, Actel Corporation, 650.318.4614
