Enhanced Actel Libero IDE Enables Faster Timing Closure and Performance Improvements for ProASICPLUS FPGAs
Libero v5.2 IDE Includes ChainBuilder Software to Ease In-System
Programming; Linux Support Added to Actel's Designer Software
MOUNTAIN VIEW, Calif., February 02, 2004 —
Actel Corporation (Nasdaq:
ACTL) today announced it has enhanced its Libero™ integrated design
environment (IDE) to provide customers with faster timing closure when
using the company's successful flash-based ProASICPLUS field-programmable
gate arrays (FPGAs). With tighter integration between the Timer engine
and timing-driven place and route, the Libero v5.2 IDE offers push-button
results that often meet or exceed customer requirements, thereby reducing
the number of design iterations required to achieve timing closure. Further,
Actel's Libero v5.2 IDE, together with the enhanced Magma PALACE™ v1.1
physical synthesis software, enables designers using ProASICPLUS FPGAs
to achieve an average performance boost of 20 percent. Other new features
of the Libero IDE include the addition of Actel's ChainBuilder software,
which enables programming or testing of Actel's ProASICPLUS FPGAs
when included in a daisy chain of devices, and support for the Linux
Red Hat 7.1 platform for Actel's Designer physical design tool suite
within the Libero IDE.
"As FPGA designs grow in size and complexity, customers often face
extreme challenges in obtaining timing closure. Using Actel's Libero
v5.2 IDE along with Magma's PALACE v1.1 physical synthesis software,
designers can often quickly and easily realize timing closure without
tweaking and reiterating, which reduces design costs and design cycles," said
Saloni Howard-Sarin, director of tools marketing at Actel.
Howard-Sarin continued, "In line with our commitment to deliver
best-in-class tools to our customers, we are also pleased to offer the
new ChainBuilder tool within Libero to enable designers to automate and
simplify a formerly cumbersome and error-prone manual identification
process. And with Actel Designer software available on the Linux RedHat
7.1 platform, we expect that a broader base of the worldwide design community
will be able to migrate to Actel's successful ProASICPLUS FPGAs."
Enhancements to Actel Libero IDE
The tighter integration between the Timer engine and timing-driven place
and route gives higher priority to user constraints, increasing designer
control over place and route to help converge on timing requirements.
Further, new improvements to Actel's routing algorithms also contribute
to the performance improvements for ProASICPLUS devices. Additionally,
Magma's PALACE physical synthesis software has also been enhanced to
provide an additional 10 percent performance improvement on average for
the ProASICPLUS devices. Integrated with Actel's Libero IDE,
the simple-to-use PALACE tool accepts an interpreted netlist and makes
optimized placement decisions based on constraints and detailed design
and interconnect modeling.
Behrooz Zahiri, director of marketing, Magma Design Automation, said, "Actel's
ProASICPLUS FPGAs represent the leading edge of programmable
logic design, both in features and performance. We are pleased to equip
our mutual customers with a physical synthesis tool that helps to deliver
the performance and quality of results needed for their complex FPGA
designs. To date, Magma and Actel have enabled designers to realize a
cumulative 25-30 percent performance improvement when using PALACE on
Actel's ProASICPLUS FPGAs."
In the past, developers have had to manually identify devices and their
order within a chain. Now, the Libero and Designer tool suites feature
Actel's ChainBuilder software, which allows for the creation of a concatenated
STAPL file from a graphical user interface. A programmer, such as Actel's
FlashPro, can then utilize the file to program or test a daisy chain
of FPGAs, custom integrated circuits (ICs), microcontrollers and/or microprocessors.
Additionally, with ChainBuilder, specific Actel FPGAs can be isolated
from other FPGAs, both Actel and non-Actel devices, and programmed individually
or in parallel via a common header attached to the JTAG chain.
Companies are adopting Linux in an increasingly open-source world. To
broaden its platform support for its tool suites, Actel is now supporting
Designer software on Linux Red Hat 7.1. Actel plans to provide support
for additional Linux platforms over the next year.
To improve ease of use and reduce development time, especially for designers
who are less familiar with the Libero software, Actel has added a new
Project Manager Graphical Interactive Flow Window to make the design
flow more intuitive and provide a step-by-step guide through the design
process.
About the Libero Integrated Design Environment
Actel's Libero v5.2 IDE offers the latest and best-in-class tools from
EDA partners Mentor Graphics, SynaptiCAD, Synplicity and Magma Design
Automation, as well as custom developed tools from Actel, integrated
into a single FPGA development package. Actel offers one-stop shopping
for its customer's EDA tool needs by means of a powerful design manager
that keeps track of design files and seamlessly manages the interoperability
issues that typically arise when using tools from different vendors.
The Libero tool suite also supports mixed-mode design entry input, giving
designers the choice of mixing either high-level VHDL or Verilog HDL
language blocks with schematic modules within a design.
Pricing and Availability
The Actel Libero v5.2 IDE is available in mid-February in four editions:
Platinum PS (physical synthesis), Platinum, Gold and Silver. Libero Silver
may be used by qualified designers for one year free of charge via the
Actel Web site. Pricing for the Platinum PS version, including the Actel
edition of Magma's PALACE tool, begins at $3495 for a one-year license.
An evaluation version of Libero Platinum PS may be used by qualified
designers for 45 days free of charge. Pricing for Libero Platinum and
Libero Gold is $2495 and $595, respectively. A one-year standalone license
for the PALACE software for use with Actel's Designer is available from
Actel for $1795. For further information about pricing and availability,
please contact Actel.
About Actel
Actel Corporation is a supplier
of innovative programmable logic solutions, including field-programmable
gate arrays (FPGAs) based on antifuse and flash technologies, high-performance
intellectual property (IP) cores, software development tools and design
services, targeted for the high-speed communications, application-specific
integrated circuit (ASIC) replacement and radiation-tolerant markets.
Founded in 1985, Actel employs more than 500 people worldwide. The
Company is traded on the Nasdaq National Market under the symbol ACTL
and is headquartered at 2061 Stierlin Court, Mountain View, CA, 94043-4655.
Telephone: 888-99-ACTEL (992-2835). Internet: http://www.actel.com.
Contact: Stephanie Mrus, Actel Corporation, 650.318.4614
