Agenda

Please check the website for session abstracts and other new or updated information, which will be posted as they become available.

8:30 AM – 8:45 AM	Executive Keynote John East
8:45 AM – 9:30 AM	Product Roadmap Ken O'Neill
9:30 AM – 10:00 AM	Power Matters: Challenges and Solutions Nizar Abdallah
10:00 AM – 10:30 AM	Timing Analysis and Constraints with SmartTime Tim McCarthy
10:30 AM – 10:45 AM	Break
10:45 AM – 11:30 AM	RT ProASIC3 Design Techniques Ron Evans
11:30 AM – 12:00 PM	RTAX-DSP Design Techniques Joel Landry
12:00 PM – 12:30 PM	Segmentable Globals in Actel RT Products Tim McCarthy
12:30 PM – 1:30 PM	Lunch and Special Presentation Mars Science Laboratory FPGA Overview Douglas J. Sheldon, JPL
— Go to Preferred Track Session —

1:30 PM – 2:00 PM	Block Flow in Designer Software Tim McCarthy
2:00 PM – 2:30 PM	Radiation Characterization & Mitigation of RTAX-S FPGAs Sana Rezgui
2:30 PM – 3:15 PM	Designing with RTAX-S: Applications Engineer's Viewpoint Jonathan Alexander
3:15 PM – 3:30 PM	Break
3:30 PM – 4:00 PM	Radiation Characterization & Mitigation of RT ProASIC3 Flash-Based FPGAs Sana Rezgui
4:00 PM – 4:30 PM	QML Class V Qualification and Future Product Qualification Activities Solomon Wolday
4:30 PM – 5:00 PM	RTAX-S Design Optimization Using Fast Carry and I/O Registers Vishal Aggarwal
5:00 PM – 5:30 PM	RTAX-S and Simultaneously Switching Outputs (SSO) Amal Zerrouki
— Return to General Session —

1:30 PM – 2:15 PM	Implementing System-Level DSP Algorithms in Actel FPGAs Using Synplify DSP Angela Sutton, Synopsys
2:15 PM – 2:45 PM	Using EDAC and Scrubbing to Protect SRAM in RTAX-S Steve Swanstrom
2:45 PM – 3:15 PM	High Performance Analog and Mixed Signal Solutions for Space Applications Ted Karlin, National Semiconductor
3:15 PM – 3:30 PM	Break
3:30 PM – 4:00 PM	Bus Interface IP—PCIF and MIL-STD-1553 Cameron Wade
4:00 PM – 4:30 PM	Fault Tolerant LEON3 Processor and Peripherals Sandi Habinc, Aeroflex Gaisler AB
4:30 PM – 5:00 PM	Radiation Hardened (RH) Product and ELDRS Characterization Updates Rafi Albarian, Linear Technology
5:00 PM – 5:30 PM	Reprogrammable Prototyping Solution for RT FPGAs Olga Melnikova, Aldec
— Return to General Session —

5:30 PM – 6:00 PM	Roundtable Discussions
6:00 PM – 8:00 PM	Reception